US 5,989,978 A · Shallow trench isolation of MOSFETS with reduced corner parasitic currents

Abstract

A method is described for forming MOSFETs with shallow trench isolation wherein the abrupt corners introduced by anisotropically etching the silicon trenches are modified by an oxidation step which rounds off the corners and also reduces the effect of tensile stresses caused by the densified trench filler material. The method selectively exposes the corner regions to an oxidation whereby the formation of an oxide birdsbeak modulates the corners and introduces a compressive stress component in the corner region. Several variations of the procedure are disclosed, including embodiments wherein birdsbeaks extending in both a vertical and horizontal directions from the corners are employed. The channel and gate oxide edges of MOSFETs extend to these corners. By attenuating the abrupt corners and reducing the mechanical stresses, gate oxide integrity is improved and anomalous sub-threshold currents of MOSFETs formed are abated.

Claims22

Dependent claims

A method for forming a MOSFET with shallow trench isolation on a silicon wafer comprising:

(a) providing a silicon wafer;
(b) forming a pad oxide on said wafer;
(c) depositing a first silicon nitride layer on said pad oxide;
(d) patterning said first silicon nitride layer and said pad oxide to define an opening exposing a silicon region;
(e) anisotropically etching said silicon region in said opening, thereby forming a trench;
(f) oxidizing said trench, thereby forming an oxide trench lining;
(g) depositing a second silicon nitride layer over said silicon wafer;
(h) depositing a layer of filler material over said silicon wafer, thereby filling said trench;
(i) densifying said filler material;
(j) planarizing said silicon wafer whereby said first silicon nitride layer is exposed;
(k) etching said first silicon nitride layer;
(l) etching said pad oxide;
(m) oxidizing said silicon wafer, whereby a planar oxide layer and a vertical birdsbeak oxide penetrating the upper portion of said oxide trench lining are formed;
(n) etching said planar oxide layer while retaining said birdsbeak oxide;
(o) forming a gate oxide on said silicon wafer.
(p) forming a gate over said gate oxide;
and
(q) forming source/drain regions on said silicon wafer, thereby forming a MOSFET.

15 more elements

A method for forming a MOSFET with shallow trench isolation on a silicon wafer comprising:

(a) providing a silicon wafer;
(b) forming a pad oxide on said wafer;
(c) depositing a first silicon nitride layer on said pad oxide;
(d) depositing an etch stop layer over said first silicon nitride layer;
(e) depositing a second silicon nitride layer over said etch stop layer;
(f) patterning said second silicon nitride layer, said etch stop layer, said first silicon nitride layer, and said pad oxide to define an opening exposing a silicon region;
(g) anisotropically etching said silicon region in said opening, thereby forming a trench;
(h) oxidizing said trench, thereby forming a silicon oxide trench lining;
(i) depositing a third silicon nitride layer over said silicon wafer;
(j) depositing a layer of filler material over said silicon wafer, thereby filling said trench;
(k) densifying said filler material;
(l) planarizing said silicon wafer whereby said second silicon nitride layer is exposed;
(m) etching said second silicon nitride layer and a portion of said third silicon nitride layer thereby forming an undercut in said first silicon nitride layer;
(n) oxidizing said silicon wafer, whereby an oxide pocket is formed with a birdsbeak portion extending horizontally, penetrating said pad oxide, under said first silicon nitride layer and vertically, penetrating said silicon oxide trench lining, under said third silicon nitride layer;
(o) removing said etch stop layer;
(p) removing said first silicon nitride layer;
(q) etching said pad oxide and said oxide pocket while retaining said birdsbeak portion;
(r) forming a gate oxide on said silicon wafer.
(s) forming a gate electrode over said gate oxide;
and
(t) forming source/drain regions on said silicon wafer, thereby forming a MOSFET.

18 more elements

Dependencies are inferred from the claim text.

Shallow trench isolation of MOSFETS with reduced corner parasitic currents

Life of this patent

Shallow trench isolation of MOSFETS with reduced corner parasitic currents

Life of this patent

Abstract

Claims22