Method and apparatus for automatically correcting errors detected in a memory subsystem

An apparatus for correcting corrupted data, the apparatus comprising:

• access logic to access a memory in response to memory access requests from one or more requesting agents;
• error detection logic to assert a first error signal if data read from a first location in the memory is corrupt;
• and
• correction logic to detect assertion of the first error signal and to assert in response a memory access request to the access logic to write a corrected version of the data to the first location, the correction logic comprising control logic to determine whether an access command generated by the access logic to access the memory indicates a memory read operation.

An apparatus for correcting corrupted data, the apparatus comprising:

• means for accessing a memory in response to memory access requests from one or more requesting agents;
• means for asserting a first error signal if data read from a first location in the memory is corrupt;
• and
• means for detecting assertion of the first error signal and for asserting in response a memory access request to the means for accessing to write a corrected version of the data to the first location, the means for detecting comprising means for determining whether an access command generated by the means for accessing indicates a memory read operation.

A method for correcting corrupted data comprising:

• determining whether memory accesses to a memory at specified addresses are read operations to read data values therefrom;
• if the memory accesses to the memory are read operations, storing the addresses in a storage buffer while the data values are pending output from the memory;
• determining, for each of the data values output from the memory, whether the data value has a correctable error;
• and
• writing a corrected version of the data value to a location in the memory indicated by a corresponding one of the addresses stored in the storage buffer if the data value has a correctable error.

A computer system comprising:

• a processor;
• a memory that includes a plurality of random access memory components;
• and
• a controller coupled to the processor and the memory, the controller including
• access logic to access the memory in response to requests from the processor;
• error detection logic to generate an error signal for each data value output by the memory to indicate whether the data value has a correctable error;
• and
• correction logic coupled to the access logic and to the error detection logic to request the access logic to write to the memory a corrected version of each data value indicated by the error signal to have a correctable error, the correction logic comprising control logic to determine whether an access command generated by the access logic to access the memory indicates a memory read operation.

A computer system comprising:

• a processor;
• a memory that includes a plurality of extended-data-out dynamic random access memory (EDO DRAM) components;
• and
• a controller coupled to the processor and the memory, the controller including
• access logic to access the memory in response to requests from the processor;
• error detection logic to generate an error signal for each data value output by the memory to indicate whether the data value has a correctable error;
• and
• correction logic coupled to the access logic and to the error detection logic to request the access logic to write to the memory a corrected version of each data value indicated by the error signal to have a correctable error, the correction logic comprising control logic to determine whether an access command generated by the access logic to access the memory indicates a memory read operation.

A computer system comprising:

• a processor;
• a memory that includes a plurality of synchronous dynamic random access memory (SDRAM) components;
• and
• a controller coupled to the processor and the memory, the controller including
• access logic to access the memory in response to requests from the processor;
• error detection logic to generate an error signal for each data value output by the memory to indicate whether the data value has a correctable error;
• and
• correction logic coupled to the access logic and to the error detection logic to request the access logic to write to the memory a corrected version of each data value indicated by the error signal to have a correctable error, the correction logic comprising control logic to determine whether an access command generated by the access logic to access the memory indicates a memory read operation.