Dynamic delayed transaction discard counter in a bus bridge of a computer system

A computer system comprising:

• a microprocessor coupled to a CPU bus;
• a main memory coupled to a memory bus;
• a display apparatus operatively coupled to said main memory;
• a first bus bridge coupled to provide an interface between said CPU bus, said memory bus and a first peripheral bus, wherein said first bus bridge is configured to perform a delayed read operation in response to a memory read initiated on said first peripheral bus, and wherein said first bus bridge is configured to discard delayed read data following a discard count time after said delayed read operation;
• and
• a second bus bridge coupled to provide an interface between said first peripheral bus and a second peripheral bus, wherein said second bus bridge is configured to assert a flush request control signal when said second bus bridge requires ownership of said first peripheral bus to initiate a cycle to said main memory;
• wherein said first bus bridge is configured to decrease said discard count time upon flushing pending cycles from said processor bus to said first peripheral bus in response to said flush request control signal.

A method for controlling a discard of delayed read data in a first bus bridge providing an interface between a main memory and a first peripheral bus, wherein a second bus bridge is coupled to said first peripheral bus for providing an interface between said first peripheral bus and a second peripheral bus, said method comprising:

• performing a delayed read operation in response to a memory read cycle on said first peripheral bus;
• said first bus bridge discarding delayed read data resulting from said delayed read operation following a discard count time after performing said delayed read operation;
• said second bus bridge requesting ownership of said first peripheral bus to initiate a cycle to said main memory;
• flushing pending cycles from a CPU to said first peripheral bus in response to said second bus bridge requesting ownership of said first peripheral bus;
• and
• decreasing said discard count time in response to said flushing said pending cycles.

A computer system comprising:

• a first bus interface coupled to provide an interface between a first bus and a second bus, wherein said first bus interface is configured to effectuate delayed transaction operations on said second bus, and wherein said first bus interface includes a discard counter configured to discard delayed transaction information relating to a given delayed transaction a predetermined time after said given delayed transaction is initiated on said second bus;
• and
• a second bus interface coupled to provide an interface between said second bus and a third bus;
• wherein said first bus interface is configured to decrease a discard time associated with said discard counter in response to a request for a transaction to be initiated by said second bus interface on said second bus.