Loading patent…
AssigneeWinbond Electronics Corp.I
InventorsDah-Bin Kao, Loc B. Hoang, Albert Wu, Tung-Yi Chan
Estimating the term…
A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.
A semiconductor memory array, comprising:
A method for programming a selected storage site in a semiconductor memory array having a plurality of interconnected storage sites arranged in intersecting rows and columns, each of said storage sites being a transistor having a drain region on a first side, a source region on a second side generally opposite from said first side, a channel interposed between said drain region and said source region, and a control gate, wherein the transistors common to a column share a common elongated region connecting the drain regions of the transistors in the column to form a bit-line for the column, the transistors common to a column share a common elongated region connecting the source regions of the transistors in the column to form a source-line for the column, and the transistors common to a row share a common elongated region connecting the control gates of the transistors in the row to form a word-line for the row, comprising the steps of:
A method as recited in 9 wherein said first positive voltage is at a voltage potential higher than said third positive voltage.
A method as recited in 10 wherein said second positive voltage is at a voltage potential lower than said third positive voltage.
A method as recited in 9 wherein said first positive voltage is at about 12 volts.
A method as recited in 12 wherein said second positive voltage is at about 2 volts.
A method as recited in 13 wherein said third positive voltage is at about 5 volts.
A method for reading a selected storage site in a semiconductor memory array having a plurality of interconnected storage sites arranged in intersecting rows and columns, each of said storage sites beings a transistor having a drain region on a first side, a source region on a second side generally opposite from said first side, a channel interposed between said drain region and said source region, and a control gate, wherein the transistors common to a column share a common elongated region connecting the drain regions of the transistors in the column to form a bit-line for the column, the transistors common to a column share a common elongated region connecting the source regions of the transistors in the column to form a source-line for the column, and the transistors common to row share a common elongated region connecting the control gates of the transistors in the row to form a word-line for the row, comprising the steps of:
A method as recited in 15 wherein said first positive voltage is at a voltage potential higher than said second positive voltage.
A method as recited in 16 wherein said second and third voltages are about the same voltage potential level.
A method as recited in 15 wherein said first positive voltage is at about 4 volts.
A method as recited in 18 wherein said second positive voltage is at about 2 volts.
A method as recited in 19 wherein said third positive voltage is at about 2 volts.
A method for erasing storage sites in a selected row sharing a common word line in a semiconductor memory array having a plurality of interconnected storage sites arranged in intersecting rows and columns, each of said storage sites being a transistor having a drain region on a first side, a source region on a second side generally opposite from said first side, a channel interposed between said drain region and said source region, a floating gate overlying at least a portion of said channel, and a control gate, said floating gate being separated from said channel by a first insulating layer and including at least one ridge having a sharp edge formed on a top surface thereof, said control gate being separated from said floating gate by a second insulating layer, said ridge for facilitating electron tunneling from said floating gate to said control gate during erasing, the transistors common to a column sharing a common elongated region connecting the drain regions of the transistors in the column to form a bit-line for the column, the transistors common to a column sharing a common elongated region connecting the source regions of the transistors in the column to form a source-line for the column, and the transistors common to row sharing a common elongated region connecting the control gates of the transistors in the row to form a word-line for the row, comprising the steps of:
A method as recited in 21 wherein said first positive voltage is approximately equal to 14 volts.
Dependencies are inferred from the claim text.