US 5,986,914 AGranted

Active hierarchical bitline memory architecture

AssigneeSTMicroelectronics S.r.l.

InventorDavid Charles McClure

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Abstract

In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.

Claims61

Dependent claims

A partitioned memory array, comprising:

a master bitline;
a plurality of serially connected local bitline segments of a local bitline connected to a plurality of memory cells and with each local bitline segment of the plurality of serially connected local bitline segments connected in parallel to the master bitline, wherein the plurality of memory cells are suitable for use during both a read operation and a write operation;
a plurality of interface circuits, wherein each interface circuit connects the master bitline to a local bitline segment of the plurality of serially connected local bitline segments, comprising one or more write interface circuits to connect the master bitline to the local bitline segment during the write operation and one or more read interface circuits to connect the master bitline to the local bitline segment during the read operation;
and
a plurality of local select signals, wherein a read local select signal of the plurality of local select signals is capable of selecting the local bitline segment to be coupled to the master bitline by a read interface circuit of the one or more read interface circuits during the read operation and wherein a write local select signal of the plurality of local select signals is capable of selecting the local bitline segment to be coupled to the master bitline by a write interface circuit of the one or more write interface circuits during the write operation.

2 more elements

Dependencies are inferred from the claim text.