.SIGMA.-.DELTA. modulator-controlled phase-locked-loop circuit
AssigneeTelefonaktiebolaget L M Ericsson (publ)
InventorH.ang.kan Bengt Eriksson
Life of this patent
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Abstract
A .SIGMA..DELTA. modulator-controlled, phase-locked-loop circuit, and an associated method, generates a frequency-regulated signal which does not exhibit undesired tones. Dithering signals are generated and are provided to a .SIGMA..DELTA. modulator. The .SIGMA..DELTA. modulator forms a division-factor control signal used to control the division factor of a frequency divider forming a portion of the PLL circuit. The dithering signals applied to the .SIGMA..DELTA. modulator reduce the likelihood that the .SIGMA..DELTA. modulator shall enter a limit cycle and generate repetitive output signals.
Claims31
In a PLL (phase-locked-loop) circuit having a VCO (voltage-controlled oscillator) for generating a VCO output signal, the VCO regulated by an input reference signal and the VCO output signal coupled to a feedback loop having a frequency divider for dividing the VCO output signal by a selected division-factor, an improvement of apparatus for generating a division-factor control signal for application to the frequency divider, values of the division-factor control signal determinative of the selected division factor, said apparatus comprising:
- a dither signal generator for generating dither signals of at least pseudo-random values;
- a noise shaper coupled to receive sequences of frequency input signals having a first signal characteristic and to receive the dither signals generated by said dither signal generator, said noise shaper for generating responsive to summed values formed therefrom, the division-factor control signal, the division-factor control signal formed of division-factor control signals having a second signal characteristic;
- and
- wherein said dither signal generator comprises a memory device having memory locations for storing a plurality of values therein, the memory locations accessed in at least a pseudo-random manner, the values stored in the memory locations accessed in the pseudo-random manner forming at least portions of the dither signals.
A method of regulating operation of a VCO (voltage-controlled oscillator) which generates a VCO output signal and which forms a portion of a PLL (phase-locked loop) circuit, the PLL circuit coupled to receive an input reference signal, said method comprising the steps of:
- coupling a frequency divider in a feedback loop to the VCO;
- applying dither signals at an input of a quantizer of a .SIGMA..DELTA. modulator;
- generating a division-factor control signal at the .SIGMA..DELTA. modulator, the .SIGMA..DELTA. modulator operable to shape at least noise components of summed values formed of frequency input sequences with the dither signals into desired characteristics;
- applying the division-factor control signal to the frequency divider coupled during said step of coupling, values of the division-factor control signal determinative of a division-factor by which the frequency divider divides a feedback signal provided to the frequency divider;
- dividing the feedback signal by the division factor to form a frequency-divided signal;
- determining phase differences between the frequency-divided signal and the input reference signal;
- and
- adjusting oscillation of the VCO responsive to phase differences determined during said step of determining.
In a PLL (phase-locked-loop) circuit having a VCO (voltage-controlled oscillator) for generating a VCO output signal, the VCO regulated by an input reference signal and the VCO output signal coupled to a feedback loop having a frequency divider for dividing the VCO output signal by a selected division-factor, an improvement of apparatus for generating a division-factor control signal for application to the frequency divider, values of the division-factor control signal determinative of the selected division factor, said apparatus comprising:
- a dither signal generator for generating dither signals of at least pseudo-random values;
- a noise shaper coupled to receive sequences of frequency input signals having a first signal characteristic and to receive the dither signals generated by said dither signal generator, said noise shaper for generating responsive to summed values formed therefrom, the division-factor control signal, the division-factor control signal formed of division-factor control signals having a second signal characteristic;
- and
- wherein:
- said noise shaper comprises a .SIGMA..DELTA. modulator;
- said .SIGMA..DELTA. modulator comprises a multi-order .SIGMA..DELTA. modulator;
- said .SIGMA..DELTA. modulator comprises a third-order, feed forward .SIGMA..DELTA. modulator formed of a first, second-order .SIGMA..DELTA. modulator and a second, second-order .SIGMA..DELTA. modulator connected together in a cascaded connection;
- and
- the first, second-order .SIGMA..DELTA. modulator comprises a first quantizer and the second, second-order .SIGMA..DELTA. modulator comprises a second quantizer, and wherein dithering signals are summed together with frequency-value input signals at each of the first and second .SIGMA..DELTA. modulators, respectively, prior to application to the first and the second quantizers, respectively.
A radiotelephonic device having a division-factor selection signal generator circuit for generating a division-factor control signal, values of the division-factor control signal, when applied to a frequency divider, determinative of a division factor of the frequency divider, the division-factor selection signal generator circuit of said radiotelephonic device comprising:
- a dither signal generator for generating dither signals of at least pseudo-random values;
- a noise shaper coupled to receive frequency input signals having a first signal characteristic and to receive the dither signals generated by said dither signal generator, said noise shaper for generating, responsive to the dither signals and the frequency input signals, the division-factor control signal, the division-factor control signal formed of division-factor control sequences having a second signal characteristic;
- and
- wherein said dither signal generator comprises a memory device having memory locations for storing a plurality of values therein, the memory locations accessed in at least a pseudo-random manner, the values stored in the memory locations accessed in the pseudo-random manner forming at least portions of the dither signals.
A method for generating a division-factor control signal for application to a frequency divider of a PLL (phase-locked-loop) circuit, said method comprising the steps of:
- generating dither signals formed of at least pseudo-random values, said step of generating dither signals comprising the steps of accessing in at least a pseudo-random manner a memory device having memory locations for storing a plurality of values therein and forming at least portions of the dither signals based, at least in part, on the plurality of values accessed from the memory locations;
- combining the dither signals generated during said step of generating with frequency input signals to form combined values, the frequency input signals having first characteristics;
- and
- quantizing the combined values formed during said step of combining to form quantized values, the quantized values having second characteristics, and the quantized values forming the division-factor control signal.
A method of regulating operation of a VCO (voltage-controlled oscillator) which generates a VCO output signal and which forms a portion of a PLL (phase-locked loop) circuit, the PLL circuit coupled to receive an input reference signal, said method comprising the steps of:
- coupling a frequency divider in a feedback loop to the VCO;
- generating a division-factor control signal at a .SIGMA..DELTA. modulator, the .SIGMA..DELTA. modulator operable to shape at least noise components of summed values formed of frequency input sequences with dither signals into desired characteristics, the dither signals derived from, at least in part, values retrieved from memory locations of a memory accessed pseudo-randomly;
- applying the division-factor control signal to the frequency divider coupled during said step of coupling, values of the division-factor control signal determinative of a division-factor by which the frequency divider divides a feedback signal provided to the frequency divider;
- dividing the feedback signal by the division factor to form a frequency-divided signal;
- determining phase differences between the frequency-divided signal and the input reference signal;
- and
- adjusting oscillation of the VCO responsive to phase differences determined during said step of determining.
In a PLL (phase-locked-loop) circuit having a VCO (voltage-controlled oscillator) for generating a VCO output signal, the VCO regulated by an input reference signal and the VCO output signal coupled to a feedback loop having a frequency divider for dividing the VCO output signal by a selected division-factor, an improvement of apparatus for generating a division-factor control signal for application to the frequency divider, values of the division-factor control signal determinative of the selected division factor, said apparatus comprising:
- a dither signal generator for generating dither signals of at least pseudo-random values;
- and
- a noise shaper coupled to receive sequences of frequency input signals having a first signal characteristic and to receive the dither signals generated by said dither signal generator, said noise shaper including:
- at least one filter for filtering the sequences of frequency input signals and generating a filtered signal formed of filtered signals having a second signal characteristic,
- at least one summer for summing the dither signals and the filtered signals to produce summed values, and
- at least one quantizer for quantizing the summed values,
- whereby said noise shaper generates responsive to the summed values, the division-factor control signal, the division-factor control signal formed of division-factor control signals having a third signal characteristic.
A radiotelephonic device having a division-factor selection signal generator circuit for generating a division-factor control signal, values of the division-factor control signal, when applied to a frequency divider, determinative of a division factor of the frequency divider, the division-factor selection signal generator circuit of said radiotelephonic device comprising:
- a dither signal generator, said dither signal generator generating dither signals of at least pseudo-random values;
- and
- a noise shaper, said noise shaper including a filter and a quantizer, the filter coupled to receive frequency input signals having a first signal characteristic and to produce filtered signals having a second signal characteristic, the quantizer coupled to receive values derived from both the dither signals and the filtered signals, said noise shaper generating, responsive to the received values, the division-factor control signal, the division-factor control signal formed of division-factor control sequences having a third signal characteristic.
A method for generating a division-factor control signal for application to a frequency divider of a PLL (phase-locked-loop) circuit, said method comprising the steps of:
- generating dither signals formed of at least pseudo-random values;
- receiving frequency input signals, the frequency input signals having first characteristics;
- filtering the frequency input signals to produce filtered signals having second characteristics;
- combining the dither signals generated during said step of generating with the filtered signals to form combined values;
- and
- quantizing the combined values formed during said step of combining to form quantized values, the quantized values having third characteristics and forming the division-factor control signal for application to the frequency divider.
Dependencies are inferred from the claim text.