Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings

A method for fabricating bonding pads for integrated circuits comprising the steps of:

• providing a semiconductor substrate having devices formed from a patterned polysilicon layer in device areas that are surrounded by a field oxide isolation, and further having a multilevel of patterned conducting layers, with alternating insulating layers having interconnecting conducting plugs to provide electrical interconnections between said patterned conducting layers for said devices;
• depositing a bond-pad conducting layer over the topmost insulating layer of said multilevel and over said interconnecting conducting plugs;
• depositing a capping layer composed of tungsten over said bond-pad conducting layer to provide an etch-stop layer;
• patterning said capping layer and said bond-pad conducting layer to form bonding pads for integrated circuits;
• depositing a passivation layer over said bonding pads;
• selectively etching contact openings in said passivation layer over said bonding pads wherein said capping layer prevents said selective etching from etching said bonding pads, while concurrently etching fuse openings through said passivation layer and said insulating layers of said multilevel and leaving a portion of said insulating layers over portions of said underlying patterned polysilicon layer that serve as fuses;
• selectively etching said capping layer in said contact openings to complete said bonding pads and said fuse openings for said integrated circuits.