US 5,982,675 A · Cache memory and microprocessor having the same

Abstract

A memory unit has, for each bit line, a latch circuit for holding data read out of a memory cell until the next access takes place, and a comparator for comparing data to be written into the memory cell and the data held in the latch circuit. If read and write operations consecutively occur at the same address and if some data bits to be written agree with corresponding data bits held in the latch circuits, there is no need of writing data for these bits. Accordingly, the write operation is disabled for these bits and is enabled only for bits that show disagreement between the data to be written and the data stored in the latch circuits. The power consumption of memory cells in a write operation is far greater than that in a read operation. Accordingly, omitting unnecessary write operations in the manner mentioned above greatly reduces the power consumption of the memory unit and the power consumption of a microprocessor that employs the memory unit.

Claims24

Dependent claims

A memory unit comprising:

(a) a memory cell array having memory cells that are arranged in an X-Y matrix and are connected to predetermined bit lines;
(b) latch circuits arranged for the bit lines, respectively, for holding data read out of the memory cells through the bit lines;
(c) comparators arranged for the bit lines, respectively, for comparing data to be written into the memory cells with data held in the latch circuits and determining whether or not they agree with each other bit by bit;
and
(d) write control circuits arranged for the bit lines, respectively, for controlling a write operation of the memory cells according to comparison results provided by the comparators bit by bit,
wherein, if read and write operations consecutively occur on the same bits and if the comparators determine that some bits of data to be written by the write operation agree with data held in the latch circuits, the write control circuits corresponding to the agreed bits disable the write operation for the bits.

3 more elements

A cache memory comprising:

(a) a tag memory cell array having tag memory cells that are arranged in an X-Y matrix and are connected to predetermined tag bit lines;
(b) a data memory cell array having data memory cells that are arranged in an X-Y matrix and are connected to predetermined data bit lines;
(c) tag latch circuits arranged for the tag bit lines, respectively, for holding tag data read through the tag bit lines;
(d) tag comparators arranged for the tag bit lines, respectively, for comparing data to be written with tag data held in the tag latch circuits;
and
(e) tag write control circuits arranged for the tag bit lines, respectively,
wherein, in a read operation, the tag latch circuits hold tag data read out of the tag memory cell array, and in a refill operation that follows the read operation, the tag comparators compare data to be written with the tag data held in the tag latch circuits bit by bit, and if any of the tag comparators shows agreement as a comparison result, the tag write control circuit corresponding to the tag comparator in question disables a write operation for the corresponding tag bit line.

4 more elements

A microprocessor comprising:

(a) a CPU;
(b) a cache controller;
(c) a bus interface unit connected to an external memory;
and
(d) a cache memory having:
a tag memory cell array having tag memory cells that are arranged in an X-Y matrix and are connected to predetermined tag bit lines;
a data memory cell array having data memory cells that are arranged in an X-Y matrix and are connected to predetermined data bit lines;
tag latch circuits arranged for the tag bit lines, respectively, for holding tag data read through the tag bit lines;
tag comparators arranged for the tag bit lines, respectively, for comparing data to be written with tag data held in the tag latch circuits;
and
tag write control circuits arranged for the tag bit lines, respectively,
wherein, in a read operation, the tag latch circuits hold tag data read out of the tag memory cell array, and in a refill operation that follows the read operation, the tag comparators compare data to be written with the tag data held in the tag latch circuits bit by bit, and if any of the tag comparators shows agreement as a comparison result, the tag write control circuit corresponding to the tag comparator in question disables a write operation for the corresponding tag bit line.

9 more elements

Dependencies are inferred from the claim text.

Cache memory and microprocessor having the same

Life of this patent

Cache memory and microprocessor having the same

Life of this patent

Abstract

Claims24