Linearizing offset cancelling white balancing and gamma correcting analog to digital converter for active pixel sensor imagers with self calibrating and self adjusting properties

A semiconductor integrated Analog to Digital (A/D) converter circuit comprising:

• an analog comparator;
• a digital counter;
• a reference ramp generator;
• a constant current source;
• and
• a signal generator;
• wherein
• the analog comparator compares the output of the reference ramp generator to an analog input signal;
• the digital counter counts cycles of an input clock signal;
• the reference ramp generator is driven by the constant current source;
• the reference ramp generator responds to the driving constant current source by generating a predetermined monotonic function of time (ramp function);
• the initial value of the ramp function is an operating variable;
• the value of the constant current source is an operating parameter;
• the A/D converter operating cycle has at least two phases, a reset phase and an active phase;
• the ramp generator and the digital counter are simultaneously initialized during the reset phase;
• the ramp generator comprises a scaled replica of the signal generator circuit;
• the signal generator generates an output in response to a physical stimulus continuously applied to the converter circuit;
• and
• an output of the A/D converter is a count attained by the digital counter during a time interval beginning with the onset of the active phase of an A/D converter operating cycle, and ending on an analog comparator output transition.

A semiconductor integrated circuit comprising an Analog to Digital (A/D) converter circuit of the single slope integration type, wherein said A/D converter comprises:

• an analog comparator subcircuit having an analog signal input terminal, an analog reference input terminal, and a digital signal output terminal;
• a digital counter subcircuit, having a clock signal input terminal, a control enable input terminal, and a control reset input terminal, wherein a phase of a clock generator circuit generating said clock signal is a predetermined function of time;
• a ramp generator subcircuit having a signal input terminal, a signal output terminal, and a control reset input terminal;
• a reference constant current generator;
• and wherein the digital output of the analog comparator circuit is connected to the enable terminal of the digital counter subcircuit;
• the output of the ramp generator subcircuit is connected to the reference input terminal of the analog comparator subcircuit;
• the input terminal of the ramp generator is connected to the reference constant current generator;
• the subcircuits and the current source share a common signal reference node (circuit ground node);
• the input terminal of the A/D converter is the input terminal of the analog comparator subcircuit;
• the response of the ramp generator circuit to the input constant current generated by the reference constant current generator is a predetermined monotonic function of time (ramp signal);
• an A/D converter operating cycle has at least two phases, a reset phase and a ramping phase;
• the digital counter subcircuit and the ramp generator subcircuit are simultaneously reset during the reset phase of the operating cycle;
• at the onset of the ramping phase of an operating cycle, the ramp generator is enabled to generate output simultaneously as the digital counter is enabled to count clock signal pulses;
• the ramp generator output assumes a predetermined value at the beginning of the ramping phase;
• the value assumed by the output of the ramp generator at the beginning of the ramping phase is an operating variable of the A/D converter circuit;
• the value of the constant current source connected to the input of the ramp generator is an operating variable of the A/D converter circuit;
• an output of the A/D converter circuit is a count of the digital counter subcircuit;
• and
• an output of the A/D converter circuit is a count attained by the digital counter in a time interval beginning with an onset of a ramping phase of an operating cycle and ending within the same ramping phase on the occasion of a transition of the digital output of the analog comparator subcircuit.

A signal processing circuit highly immune to manufacturing variations and variations in operating conditions for outputting a digital word corresponding to stimulus applied to a photo-sensor device, said circuit comprising:

• an analog integrator circuit responsive to said photo-sensor device for outputting a first signal representative of said device;
• a reference signal generator circuit responsive to a constant current source for generating a second signal, said second signal being a ramp signal and the reference signal generator being a scaled replica of the analog integrator circuit;
• and
• an output circuit including a comparator for receiving said first and said second signals and for comparing the level of said first signal against the level of said second signal, said output circuit also including a counter for generating said digital word representative of a time interval defined by a start signal and an end signal, said end signal representing a transition of the output of the comparator.