Multi-loop .SIGMA. .DELTA. analog to digital converter

A sigma-delta analog-to-digital converter comprising:

• a plurality of loops coupled in cascade, each loop including at least one delay circuit, wherein each delay circuit comprises an amplifier and two or more signal paths, each signal path comprising:
• a first switch;
• a capacitor coupled to said first switch;
• a second switch coupled to said capacitor and an AC ground;
• a third switch coupled to said first switch and an output of said amplifier;
• and
• a fourth switch coupled to said second switch and an input of said amplifier;
• wherein each signal path in a particular delay circuit is clocked by a set of clock signals having clock phases unique from those of other signal paths in the particular delay circuit.

A sigma-delta analog-to-digital converter comprising:

• a plurality of loops coupled in cascade, each loop including at least one delay cell and summer circuit, wherein each delay cell and summer circuit comprises an amplifier and two or more signal paths, each signal path comprising:
• a first switch;
• a first capacitor coupled to said first switch;
• a second switch coupled to said first capacitor and said AC ground;
• a third switch coupled to said first switch and said output of said loop in which said delay cell and summer circuit reside;
• a second capacitor coupled to said first capacitor;
• a fourth switch coupled to said second switch and an inverting input of said amplifier;
• a fifth switch coupled to said second capacitor and said n-inverting output of said amplifier;
• and
• a sixth switch coupled to said second capacitor and an inverting output of said amplifier within said delay circuit of said resonator section.

A sigma-delta analog-to-digital converter comprising:

• a plurality of loops coupled in cascade, wherein each loop includes a quantizer implemented with two comparators, wherein one comparator is clocked by a switching clock having a first phase and another comparator is clocked by a switching clock having a second phase, and wherein said comparators provide differential outputs;
• at least one feed-forward gain element, one gain element coupled between each pair of sequential loops;
• and
• a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

A bandpass sigma-delta analog-to-digital converter comprising:

• two or more loops coupled in cascade, each loop including a plurality of discrete delay elements;
• a feed-forward gain element, one gain element coupled between each pair of adjacent loops;
• and
• a noise cancellation logic coupled to each loop, said noise cancellation logic providing a converter output.

A sigma-delta analog-to-digital converter comprising:

• two or more loops coupled in cascade;
• and
• at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops,
• wherein a bias current of at least one of said two or more loops can be adjusted based on a required dynamic range.

A sigma-delta analog-to-digital converter comprising:

• two or more loops coupled in cascade;
• and
• at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops,
• wherein at least one of said two or more loops can be disabled based on a required dynamic range.