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AssigneeThe Regents of the University of California
InventorsChenming Hu, Mansun John Chan, Hsing-Jen Wann, Ping Keung Ko
Estimating the term…
An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.
A silicon-on-insulator field effect transistor for use in an electrostatic discharge protection circuit comprising
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Characterised by the electrodes: characterised by the shapes, relative sizes or dispositions of the gate electrodes
Of FETs having insulated gates [IGFET]: forming self-aligned punch-through stoppers or threshold implants under gate regions
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon
For preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect:…
Term ended 9 Nov 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention relates generally to semiconductor devices, and more particular the invention relates to field effect devices fabricated in silicon-on-insulator structures.
Silicon-on-insulator (SOI) technology employs a layer of semiconductor material overlying an insulation layer on a supporting bulk wafer. The structure can be formed by a number of well-known techniques, such as zone melting and recrystallization (ZMR), separation by implanted oxygen (SIMOX), or Bonded and Etchback (BESOI). Typically, the structure comprises a film of monocrystalline silicon on a buried layer of silicon oxide in a monocrystalline silicon substrate.
Field effect transistors such as MOSFETs fabricated in the silicon film of an SOI structure have many advantages over MOSFETs fabricated on the traditional bulk silicon substrates including resistance to short-channel effect, steeper subthreshold slopes, increased current drive, higher packing density, reduced parasitic capacitance, and simpler processing steps. In the past, the range of SOI applications has been limited due to high cost and inferior crystalline quality of SOI wafers. However, recent advancements in the SOI silicon film quality, buried oxide quality, and manufacturing throughput have opened the door to a multitude of ultra large scale integration (ULSI) applications. Combined with the continually increasing cost of bulk silicon submicron integrated circuit processes and the lower complexity/cost of SOI integrated circuit processes, SOI technology shows great potential to become the low cost mainstream production technology.
FIG. 1 is a plot of I-V characteristics for a non-fully-depleted SOI device.
FIG. 2 is a plot of I-V characteristics for a fully-depleted SOI device.
FIG. 3 is a section view of an SOI MOSFET in accordance with one embodiment of the invention.
Features of the invention will be described with reference to specific nMOSFET embodiments, but it will be appreciated that the invention applies to pMOSFETs as well.
Referring to FIG. 3, an nMOSFET having a low barrier body contact source region in accordance with the invention is illustrated in cross-section. As in a typical SIMOX structure, a silicon substrate 10 has a buried silicon oxide layer 12 therein with the transistor fabricated in an overlying monocrystalline silicon film. The transistor includes an N.sup.+ doped drain region 14 and an N.sub.+ doped source region 16 formed over a P doped body contact 18. P.sub.+ region 20 abutting the source 16 and body contact 18 provides a current path for the impact ionization current accumulated in region 18 near the source/body junction. The source region 16 and drain region 14 are separated by a channel region 22 with a polysilicon gate contact 24 overlying the channel region 22 and insulated therefrom by silicon oxide. Metal or polysilicon interconnect lines 26, 28 are interconnected with the source and drain, respectively, with the P.sub.+ region 20 also connected to the source contact line 26.
The P region 18 underlying the source region, either neutral or depleted, provides a low resistance path to collected hole current generated by impact ionization, junction leakage, and GIDL. The P implant for the underlying P region 18 is on the order of 1.times.10.sup.14 to 1.times.10.sup.16 dopant atoms per cm.sup.-2. The N+ implant for the source and drain is higher in dopant concentration with a lower implant energy level to form the shallower N+ doped regions. The P- doped low barrier contact can be provided under both the source and drain for a simpler fabrication process. The P+ contact 20 is formed after the N+ implant.