Damascene isolation of CMOS transistors

A CMOS isolation method for a silicon substrate containing N well and P well regions, accomplished by creating a plurality of thick field oxide regions adjacent to thin gate oxide regions, wherein the N well and P well regions have concentrations of N or P type dopant implanted into the silicon substrate only below the thick oxide regions, comprising the steps of:

• a) coating over the substrate with a first thin layer of SiO.sub.2, with a much thicker layer of amorphous Si over the thin layer of SiO.sub.2, and with a first layer of photoresist;
• b) patterning the first layer of photoresist over the thicker layer of amorphous Si to cover the N well regions, and to cover portions of the P well regions where NMOS transistors are formed;
• c) implanting an acceptor dopant to a depth approximately equal to the amorphous Si thickness, with a concentration significantly greater than the P well concentration at an interface between the silicon substrate and the thin layer of SiO.sub.2 ;
• d) etching anisotropically the amorphous Si to the underlying thin layer of SiO.sub.2 ;
• e) removing the first photoresist and applying a second photoresist;
• f) patterning the second photoresist to cover the P well regions, and to cover the portions of the N well regions where PMOS transistors are formed;
• g) implanting a donor dopant to a depth approximately equal to the amorphous Si thickness, with a concentration significantly greater than the N well concentration at an interface between the silicon substrate and the thin layer of SiO.sub.2 ;
• h) etching anisotropically the amorphous Si to the underlying thin layer of SiO.sub.2 ;
• i) removing the second photoresist;
• j) depositing SiO.sub.2 to a thickness greater than the amorphous Si thickness;
• k) chemical mechanical polishing the SiO.sub.2 to a height equal to the amorphous Si thickness;
• l) removing the layer of amorphous Si.