Method of time multiplexing a programmable logic device

A programmable logic device that is programmable in a plurality of configurations, the programmable logic device comprising:

• a plurality of micro-registers, each micro-register being configured to simultaneously store a plurality of intermediate logic states associated with different configurations of the programmable logic device;
• a plurality of output selectors, each of the output selectors being configured to selectively route intermediate logic states from a corresponding micro-register;
• and
• a plurality of pipeline latches, each of the pipeline latches being configured to store intermediate logic states routed by a corresponding output selector.

A programmable logic device comprising:

• a configurable logic block having a sequential logic element;
• an interconnect structure for interconnecting said configurable logic block;
• a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure;
• a storage device configured to simultaneously store a plurality of intermediate logic states associated with different configurations of said configurable logic block;
• a latch coupled to an input terminal of the storage device;
• and
• a selector element having input terminals coupled to the sequential logic element and the storage device, and an output terminal coupled to the latch.

A programmable logic device comprising:

• a configurable logic block;
• an interconnect structure for interconnecting said configurable logic block;
• a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure;
• a storage device for storing a plurality of intermediate logic states of said configurable logic block;
• a latch coupled to an input terminal of the storage device;
• and
• a multiplexer which is programmable to couple an output terminal of the storage device to an input terminal of the latch, thereby re-circulating contents of the storage device.

A programmable logic device comprising:

• a configurable logic block;
• an interconnect structure for interconnecting said configurable logic block;
• a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure;
• and
• a storage device configured to simultaneously store a plurality of intermediate logic states associated with different configurations of said configurable logic block, wherein the storage device is located in the interconnect structure.

A programmable logic device comprising:

• a configurable logic block;
• an interconnect structure for interconnecting said configurable logic block;
• a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure;
• and
• a storage device configured to simultaneously store a plurality of intermediate logic states associated with different configurations of said configurable logic block, wherein the storage device is located in a location independent of the configurable logic block.

A method of operating a programmable logic device comprising a plurality of programmable logic elements for configuring said programmable logic device, the method comprising the steps of:

• providing a plurality of sets of N memory cells, wherein each set of N memory cells is associated with one of said programmable logic elements, and wherein the sets of memory cells form N memory slices, each of the N memory slices including one memory cell from each set of N memory cells;
• storing configuration data in at least one of the N memory slices prior to configuring the programmable logic device;
• configuring the programmable logic device in response to the configuration data;
• and then
• storing user data in all of the N memory slices.

A programmable logic device comprising:

• a plurality of programming points for controlling the configuration of the programmable logic device;
• a plurality of memory bit sets, wherein each memory bit set is coupled to a corresponding one of the programming points, each memory bit set having a plurality of configuration memory cells;
• and
• a select circuit coupled between each memory bit set and corresponding programming point, wherein each select circuit is controlled to couple one of the configuration memory cells to a programming point, and wherein the configuration memory cells in at least one of the memory bit sets store the same configuration data value, thereby configuring the associated programming point in a static mode.

A programmable logic device comprising:

• a plurality of programmable logic elements for configuring said programmable logic device;
• a plurality of sets of N memory cells, wherein each set of N memory cells is associated with one of said programmable logic elements, and wherein the sets of memory cells form N memory slices, each of the N memory slices including one memory cell from each set of N memory cells;
• and
• means for burst accessing the N memory slices.

A method of configuring a programmable logic device from a configuration memory comprising the steps of:

• configuring the programmable logic device in a first configuration using a first set of configuration data stored in a slice of the configuration memory;
• detecting an interrupt signal while the programmable logic device is configured in the first configuration;
• and
• configuring the programmable logic device in a second configuration using a second set of configuration data stored in a slice of the configuration memory, wherein the programmable logic is configured in the second configuration in response to the interrupt signal.

A method of operating a programmable logic device in a logic engine mode, the method comprising the steps of:

• configuring the programmable logic device in a first configuration by reading configuration data values from a first memory slice;
• performing logic operations with the programmable logic device in the first configuration;
• configuring the programmable logic device in a second configuration by reading configuration data values from a second memory slice;
• and
• pipelining the read access time for the second memory slice such that the configuration data values from the second memory slice are read in parallel with the logic operations of the programmable logic device in the first configuration.

A programmable logic device comprising:

• a first programming point for controlling the configuration of an interconnect of the programmable logic device;
• a second programming point for controlling the configuration of a logic of the programmable logic device;
• a first latch having an output terminal coupled to the first programming point, an input terminal coupled to a bit line, and a clock terminal coupled to receive a first clock signal;
• a second latch having an output terminal coupled to the second programming point, an input terminal coupled to the bit line, and a clock terminal coupled to receive a second clock signal;
• a first plurality of configuration memory cells coupled to the bit line and storing configuration data values for controlling the configuration of the interconnect;
• a second plurality of configuration memory cells coupled to the bit line and storing configuration data values for controlling the configuration of the logic;
• a first select circuit coupled between the bit line and the first plurality of configuration memory cells, wherein the first select circuit is controlled to couple one of the first plurality of configuration memory cells to the first latch during a first memory cycle;
• and
• a second select circuit coupled between the bit line and the second plurality of configuration memory cells,
• wherein the second select circuit is controlled to couple one of the second plurality of configuration memory cells to the second latch during a second memory cycle.

A method of configuring a programmable logic device comprising the steps of:

• providing a first set of configuration memory cells for storing a first plurality of configuration data values for configuring an interconnect of the programmable logic device;
• providing a second set of configuration memory cells for storing a second plurality of configuration data values for configuring an interconnect of the programmable logic device;
• selectively coupling one of the configuration memory cells in the first set to a bit line during a first memory cycle;
• latching a configuration data value from the bit line during the first memory cycle and providing this configuration data value to a first programming point to configure the interconnect of the programmable logic device;
• selectively coupling one of the configuration memory cells in the second set to the bit line during a second memory cycle;
• and
• latching a configuration data value from the bit line during the second memory cycle and providing this configuration data value to a second programming point to configure the logic of the programmable logic device.

A low voltage interconnect structure for an integrated circuit that operates in response to a supply voltage, the interconnect structure comprising:

• an output circuit providing an output signal that swings between zero volts and a first voltage that is greater than zero volts and less than the supply voltage;
• an interconnect circuit coupled to receive the output signal, the interconnect circuit comprising at least one turned on pass transistor;
• and
• a destination circuit coupled to receive the output signal from the interconnect circuit.

A method for coupling an output circuit to a destination circuit on an integrated circuit, the method comprising the steps of:

• providing an output signal with the output circuit that swings between zero volts and a first voltage that is greater than zero volts and less than the supply voltage;
• routing the output signal through an interconnect circuit that comprises at least one turned on pass transistor;
• and
• receiving the output signal with the destination circuit.