Digital-to-analog converter using noise-shaped segmentation

A digital-to-analog converter comprising:

• a segmentation circuit comprising:
• a digital noise shaper responsive to a stream of digital input words for producing a stream of first digital subwords;
• and
• a subtractor for subtracting each of said first digital subwords from a corresponding one of said digital input words to produce a stream of second digital subwords, wherein the sum of said first and second digital subwords is equal to the corresponding digital input word and wherein said first and second digital subwords have smaller word lengths than said digital input words;
• a first digital-to-analog converter circuit for converting each of said first digital subwords to a first analog value;
• a second digital-to-analog converter circuit for converting each of said second digital subwords to a second analog value, said first and second digital-to-analog converter circuits producing said first and second analog values, respectively, in proportion to the relative bit weights of said first and second digital subwords;
• and
• a summing circuit for summing each of said first and second analog values to produce an analog output that represents said stream of digital input words.

A segmentation tree structure comprising:

• a first segmentation circuit having an input for receiving a stream of digital input words, a first output for providing a stream of first intermediate subwords and a second output for providing a stream of second intermediate subwords;
• a second segmentation circuit having an input coupled to the first output of said first segmentation circuit for receiving said stream of first intermediate subwords, a first output for providing a stream of first output subwords and a second output for providing a stream of second output subwords;
• a third segmentation circuit having an input coupled to the second output of said first segmentation circuit for receiving said stream of second intermediate subwords, a first output for providing a stream of third output subwords and a second output for providing a stream of fourth output subwords;
• said first, second and third segmentation circuits each comprising:
• a digital noise shaper coupled between said input and said first output, and a subtractor having a first input coupled to the input of the respective segmentation circuit, a second input coupled to the first output of the respective segmentation circuit and an output coupled to the second output of the respective segmentation circuit;
• wherein the sum of each of said first, second, third and fourth output subwords is equal to the corresponding input word and wherein said first, second, third and fourth output subwords are noise-shaped when said input words are noise-shaped.

A sigma delta modulator comprising:

• a summing unit for subtracting a feedback signal from an input signal and providing a summing unit output;
• a loop filter for receiving said summing unit output and providing a filter output signal;
• a flash analog-to-digital converter for providing a digital output of n bits in response to said filter output signal;
• and
• a digital-to-analog converter responsive to said digital output for providing said feedback signal to said summing unit, said digital output comprising a stream of digital input words to said digital-to-analog converter, said digital-to-analog converter comprising:
• a segmentation circuit comprising:
• a digital noise shaper responsive to said stream of digital input words for producing a stream of first digital subwords;
• and
• a subtractor for subtracting each of said first digital subwords from a corresponding one of said digital input words to produce a stream of second digital subwords, wherein the sum of said first and second digital subwords is equal to the corresponding digital input word and wherein said first and second digital subwords have smaller word lengths than said digital input words;
• a first digital-to-analog converter circuit for converting each of said first digital subwords to a first analog value;
• a second digital-to-analog converter circuit for converting each of said second digital subwords to a second analog value, said first and second digital-to-analog converter circuits producing said first and second analog values, respectively, in proportion to the relative bit weights of said first and second digital subwords;
• and
• a summing circuit for summing each of said first and second analog values to produce an analog output that represents said stream of digital input words.