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AssigneeDigital Equipment Corporation
InventorsStephen J. Sicola, Wayne H. Umland, Thomas F. Fava, Clark E. Lubbers, Susan G. Elkington
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A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.
A method for operating between a non-mirror cache mode and one or more mirror cache modes in a cache memory system, the cache memory system having a controller, a first cache memory and a second cache memory, comprising the computer implemented steps of:
Apparatus for operating between a non-mirror cache mode and one or more mirror cache modes in a cache memory system comprising:
A method for operating between a non-mirror cache mode and one or more mirror cache modes in a cache memory system, the cache memory system having, a first cache memory and a second cache memory, comprising the computer implemented steps of:
Dependencies are inferred from the claim text.