US 5,974,438 A · Scoreboard for cached multi-thread processes

Abstract

A computer system comprising at least one processor and associated cache memory, and a plurality of registers to keep track of the number of cache memory lines associated with each process thread running in the computer system. Each process thread is assigned to one of the plurality of registers of each level of cache that is being monitored. The number of cache memory lines associated with each process thread in a particular level of the cache is stored as a number value in the assigned register and will increment as more cache memory lines are used for the process thread and will decrement as less cache memory lines are used. The number value in the register is defined as the "process thread temperature." Larger number values indicate warmer process thread temperature and smaller number values indicate cooler process thread temperature. Process thread temperatures are relative and indicate the cache memory line usage by the process threads running in the computer system at a particular level of cache. By keeping track or "score" of the number values (temperatures) in each of these registers called "scoreboard registers," the scheduler algorithm of the computer operating system may objectively determine the most advantageous order for the process threads to run and which of the processors in a multi-processor system should execute these process threads. A scoreboard register may be reassigned to a new process thread when its associated process thread has been discontinued.

Claims14

Dependent claims

A computer system having cached multi-thread processes, said system comprising:

a processor;
a cache memory connected to said processor, said cache memory having a plurality of memory lines;
a main memory connected to said cache memory;
a cache memory controller for transferring a predetermined number of bytes of information for active process threads from said main memory to said cache memory;
a plurality of scoreboard registers, each of the active process threads assigned to corresponding ones of said plurality of scoreboard registers, wherein each of the corresponding ones of said plurality of scoreboard registers store a number value representing the number of said cache memory lines that contain information for each of the plurality of active process threads;
logic circuits making available the number value in each of said plurality of scoreboard registers to a software operating system scheduler program, and
logic circuits in said cache memory controller that identify certain ones of said cache memory lines that contain information for discontinued process threads so that these certain ones may be reused before other ones of said cache memory lines containing information for active process threads are reused.

4 more elements

Dependencies are inferred from the claim text.

Scoreboard for cached multi-thread processes

Life of this patent

Scoreboard for cached multi-thread processes

Life of this patent

Abstract

Claims14