Execution processor for carrying out power calculation

An execution processor comprising:

• a first register for storing base data,
• a second register for dividing and storing exponent data into an integer region and a decimal fraction region,
• a multiplier including first and second inputs,
• third and fourth registers for storing a calculation result of said multiplier,
• a square root calculation unit,
• a fifth register for storing a calculation result of said square root calculation unit,
• a first input selector receiving an output of said first register, an output of said third register, an output of said fourth register, and a fixed value 1 for selecting any one of the received outputs according to a first input select signal to provide the same to said first input of said multiplier,
• a second input selector receiving an output of said first register, an output of said fourth register, an output of said fifth register, and a fixed value 1 for selecting any one of the received outputs to provide the same to said second input of said multiplier,
• a third input selector receiving an output of said first register and an output of said fifth register for selecting one of the received outputs according to a third input select signal to provide the same to an input of said square root calculation unit, and
• a power calculation controller checking said integer region of said exponent data for each bit while providing said first input select signal, said second input select signal, and a write enable signal to allow data writing to said third or fourth register according to the number of checking times and a value of a relevant bit, and checking said decimal fraction region of said exponent data for each bit while providing said first input signal, said second input signal, said third input signal, and a write enable signal to allow data writing to said third or fifth register according to the number of checking times and a value of a relevant bit.