Weighted capacitor array with selective grouping to form array elements
AssigneeTexas Instruments Incorporated
InventorRichard Knight Hester
Life of this patent
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Abstract
An integrated circuit for analog to digital conversion using a plurality of unit capacitors (201). The value of each unit capacitor (201) has a nonlinear spatial component determined by the location of the unit capacitor (201) on the integrated circuit. A plurality of array capacitors (101a-101e) are formed from the unit capacitors (201) such that each array capacitor (101a-101e) includes a selected group of unit capacitors (201). The unit capacitors (201) that make up each array capacitor (101a-101e) are selected based upon the nonlinear spatial component in the unit capacitance value.
Claims14
An integrated circuit for analog to digital conversion comprising:
- a plurality of unit capacitors, wherein the value of each unit capacitor has a nonlinear spatial component determined by the location of the unit capacitor on the integrated circuit;
- a plurality of array capacitors, each array capacitor comprising a selected group of unit capacitors, wherein the unit capacitors that make up each array capacitor are selected based upon the nonlinear spatial component in the unit capacitance value.
A method for arranging a number (N) of devices D on a circuit chip, wherein the devices are related to each other such that a device parameter P.sub.j for each device D.sub.j is a preselected function P.sub.j,j>1 .congruent..function.(P.sub.j-1) of the device parameter P.sub.j-1 for another device D.sub.j-1, the method for arranging comprising the steps of:
- providing a plurality of unit devices D.sub.u on the chip wherein each unit device D.sub.u has a parametric value of P.sub.u ;
- determining a linear component of variation V1 for each unit device D.sub.u wherein the V1 is function of spatial location of D.sub.u on the chip;
- determining a nonlinear component of variation V2 for each of unit devices D.sub.u wherein the V2 is function of spatial location of D.sub.u on the chip;
- and
- grouping the plurality of unit devices into N sets such that each set forms one of the number of devices D.sub.j, each set j is chosen to have a parametric value P.sub.j satisfying the equation P.sub.j,(1<j.ltoreq.N) .congruent..function.(P.sub.j-1), and at least one set comprises unit devices chosen such that .SIGMA.V2.sub.j .congruent..function.(.SIGMA.V2.sub.j-1).
A binary weighted array of capacitors comprising:
- a first set of unit capacitors having a capacitance of C.sub.u wherein C.sub.u comprises a linear spatial component and a nonlinear spatial component;
- a second set of unit capacitors having a capacitance of C.sub.2 =2 (C.sub.1);
- a third set of unit capacitors having a capacitance of C.sub.3 =2 (C.sub.2);
- a fourth set of unit capacitors having a capacitance of C.sub.4 =2 (C.sub.3);
- and
- a fifth set of unit capacitors having a capacitance of C.sub.5 =2 (C.sub.4).
Dependencies are inferred from the claim text.