Ultra high density flash memory

A memory device, comprising:

• an array of memory cells, each cell including a number of transistor formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and a number of floating gates disposed adjacent to the sides of the pillar;
• a plurality of first gate lines that are substantially parallel in a first direction, each first gate line allowing selective storage and retrieval of data on ones of the floating gates;
• a plurality of second gate lines that are substantially parallel in a second direction that is substantially orthogonal to the first direction, each second gate line allowing selective storage and retrieval of data on ones of the floating gates;
• at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells;
• and
• a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

A memory device, comprising:

• an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and more than two gates disposed adjacent to the sides of the pillar;
• a plurality of first gate lines interconnecting ones of the gates in one of the memory cells;
• a plurality of second gate lines interconnecting ones of the gates in ones of the memory cells;
• at least one first source/drain interconnection line interconnecting ones of the first source/drain regions of ones of the memory cells;
• and
• a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

A memory cell that is fabricated upon a substrate, the memory cell comprising:

• a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;
• a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;
• a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;
• a gate dielectric formed on at least a portion of the side surface of the pillar;
• more than two floating gates, each of which is substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;
• a plurality of control gates, each of which is substantially adjacent to one of the floating gates and insulated therefrom;
• and
• an intergate dielectric, interposed between each of the substantially adjacent floating and control gates.

A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising:

• a plurality of memory cells, each memory cell including:
• a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;
• a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;
• a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;
• a gate dielectric, formed on at least a portion of the side surface of the pillar;
• more than two floating gates, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;
• at least one control gate, substantially adjacent to the floating gate and insulated therefrom;
• and
• an intergate dielectric, interposed between the floating gate and the control gate;
• a plurality of first gate lines interconnecting ones of the control gates in ones of the memory cells;
• a plurality of second gate lines interconnecting ones of the control gates in ones of the memory cells;
• at least one first source/drain interconnection line interconnecting ones of the first source/drain regions of ones of the memory cells;
• and
• a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.