Translation shadow array adder-decoder circuit for selecting consecutive TLB entries

An apparatus for address translation in a processor, comprising:

• adder means for computing an effective address field indexing entries in a translation array without including a carry-in from addition of a plurality of less significant bits in an address and an offset employed to compute said effective address;
• selection means for selecting a plurality of entries within said translation array utilizing said field;
• carry generator means for calculating said carry-in from said plurality of less significant bits without adding said plurality of less significant bits in said address and said offset;
• and
• decoder means for selecting an entry within said plurality of entries utilizing said carry-in.

A combined adder/decoder in a processor including a translation array having entries indexed by an address field, comprising:

• an adder computing an address field corresponding to an index for said translation array entries without including a carry-in from addition of a plurality of less significant bits in an address and an offset employed to compute said address field and generating a signal coinciding with a plurality of entries within said translation array;
• a carry generator calculating a carry-in from said plurality of less significant bits without adding said plurality of less significant bits in said address and said offset;
• and
• a decoder receiving said signal from said adder and said carry-in from said carry generator, said decoder selecting an entry within said plurality of entries utilizing said carry-in.