Distributed memory addressing system

A method for addressing distributed memory, said method comprising;

• a) processing performed by a plurality of separate processing elements, including at least one input/output processing element, each processing element comprising at least one CPU;
• b) storing data in a shared memory;
• and
• c) communicating between the processing elements and the shared memory through a high bandwidth interface comprising a network of serial two-way electrical connections to access the requested data, processor element read/write data and embedded direction control commands, for a fixed access latency from the shared memory to every processing element and configured to provide non-blocking access to each parallel memory for each processing element and at least one dedicated two-way serial connection between each processing element to each parallel memory to communicate the data between each processing element and each parallel memory.

A method for addressing distributed memory, the method comprising of:

• a) communicating a compiled flowgraph to a node controller;
• b) determining the task to be performed via the node controller;
• c) delegating the task to a first available processing element via the node controller by communication via a node control bus to a data handler unit associate with the processing element;
• d) communicating the task from the processing elements data handler unit to the processor's CPU;
• e) decoding the task and parameters received from the node controller via the processing element;
• f) sending shared memory addressing parameters from the processing element to the shared memory via the processing element's data handler unit and the node control bus;
• g) communicating data with the processing element's CPU and the shared memory via the element's data handler unit, utilizing a high bandwidth memory interface comprising a network of serial two-way electrical connections to access the requested data, processor element read/write data and embedded direction control commands for a fixed access latency from the shared parallel memories to every processing element and configured to provide non-blocking access to each parallel memory for each processing element and
• at least one dedicated two-way serial electrical connection from each processing element to each parallel memory to communicate the data between each processing element and each parallel memory, until the task is completed;
• h) upon completion of the task, the processing element informing the node controller that the task has been completed;
• i) the node controller continuing to delegate task to additional processing elements per step (c) until all of the processing elements are utilized;
• j) when all of the processing elements are busy, the node controller waiting for a processing element to complete its task and then issuing the next task to be performed to that processing element;
• k) repeating steps (c) through (j) until all tasks have been performed;
• and
• l) performing input/output functions by input/output processors as data is needed by the distributed memory addressing system as data is needed to be output to the other devices.