Hit determination circuit for selecting a data set based on miss determinations in other data sets and method of operation

For use in a processor having a translation look-aside buffer (TLB) and an associated cache with at least first and second ways, a hit indication circuit for indicating when a hit has occurred in said first way of said cache, comprising:

• first comparing means, associated with said first way of said cache, for comparing addresses stored in said TLB and said first way and activating a first way miss signal when a cache miss is detected with respect to said first way;
• second comparing means, associated with said second way of said cache, for comparing addresses stored in said TLB and said second way and activating a second way miss signal when a cache miss is detected with respect to said second way;
• and
• means, associated with said first way of said cache, for receiving said second way miss signal and generating, in response thereto, a hit signal for said first way thereby basing a cache hit in said first way on said cache miss in said second way.

For use in a processor having a translation look-aside buffer (TLB) and an associated cache with at least first and second ways, a method of indicating when a hit has occurred in said first way of said cache, comprising the steps of:

• comparing addresses stored in said TLB and said second way;
• activating a second way miss signal when a cache miss is detected with respect to said second way;
• and
• generating, in response to said second way miss signal, a hit signal for said first way thereby basing a cache hit in said first way on said cache miss in said second way.

A computer system, comprising:

• (a) a pipelined processor having at least one execution pipeline for executing instructions, said execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages;
• (b) system memory for storing data or instructions;
• (c) a cache for storing portions of said data or ones of said instructions, said cache having at least first and second ways;
• (d) a translation look-aside buffer (TLB) for translating logical addresses to physical addresses to address said cache;
• (e) said processor including fetch logic that fetches said portions of said data or said ones of said instructions from said system memory;
• and
• (f) said processor further including a hit indication circuit for indicating when a hit has occurred in said first way of said cache, including:
• (i) a first comparator circuit, associated with said first way of said cache, that compares addresses stored in said TLB and said first way and activates a first way miss signal when a cache miss is detected with respect to said first way;
• (ii) a second comparator circuit, associated with said second way of said cache, that compares addresses stored in said TLB and said second way and activates a second way miss signal when a cache miss is detected with respect to said second way, and
• (iii) a selection circuit, associated with said first way of said cache, that receives said second way miss signal from said second comparator circuit and generates, in response thereto, a hit signal for said first way, said second comparator and selection circuits cooperating to base a cache hit in said first way on said second way miss signal.

A method of operating a computer system, comprising the steps of:

• (a) applying power to a pipelined processor having at least one execution pipeline for executing instructions, said execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages;
• (b) storing data and instructions in system memory;
• (c) fetching said data or said instructions from said system memory into a cache having at least first and second ways;
• (d) addressing said cache with a translation look-aside buffer (TLB) containing logical and physical addresses;
• and
• (e) executing said instructions in said processor, said processor further including a hit indication circuit for indicating when a hit has occurred in said first way of said cache, including:
• (i) a first comparator circuit, associated with said first way of said cache, that compares addresses stored in said TLB and said first way and activates a first way miss signal when a cache miss is detected with respect to said first way;
• (ii) a second comparator circuit, associated with said second way of said cache, that compares addresses stored in said TLB and said second way and activates a second way miss signal when a cache miss is detected with respect to said second way, and
• (iii) a selection circuit, associated with said first way of said cache, that receives said second way miss signal from said second comparator circuit and generates, in response thereto, a hit signal for said first way, said second comparator and selection circuits cooperating to base a cache hit in said first way on said second way miss signal.