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US 5,970,507 AGranted
Semiconductor memory device having a refresh-cycle program circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTetsuo Kato, Kiyohiro Furutani, Hideto Hidaka, Mikio Asakura
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.
Claims15
A semiconductor memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, a plurality of word lines each associated with one of said plurality of rows and a plurality of pairs of bit lines each associated with one of said plurality of columns;
- a plurality of sense amplifiers connected to said plurality of pairs of bit lines;
- a refresh-cycle program circuit for programming refresh cycles;
- an address generating circuit for generating refresh address signals for use in refresh operations;
- a self-refresh control circuit for incrementing a value represented by said refresh address signals at prescribed time intervals in a self-refresh mode;
- and
- select means for selecting at least one of said plurality of memory blocks in accordance with one of said refresh cycles programmed by said refresh-cycle program circuit, selecting one of said plurality of word lines of the selected memory block and activating some of said plurality of sense amplifiers associated with said selected memory block.
4 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, a plurality of word lines each associated with one of said plurality of rows and a plurality of pairs of bit lines each associated with one of said plurality of columns;
- a plurality of sense amplifiers connected to said plurality of pairs of bit lines;
- a first refresh-cycle program circuit for programming first refresh cycles in first refresh mode;
- a second refresh-cycle program circuit for programming second refresh cycles in second refresh mode;
- an address generating circuit for generating refresh address signals for use in refresh operations;
- and
- select means for selecting a first number of said memory blocks in accordance with one of said first refresh cycles programmed by said first refresh-cycle program circuit in said first refresh mode, selecting a second number memory blocks in accordance with one of said second refresh cycles programmed by said second refresh-cycle program circuit in said second refresh mode, selecting some of said plurality of word lines of the selected memory blocks and activating one of said plurality of sense amplifiers associated with the selected memory blocks.
4 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks each including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, a plurality of word lines each associated with one of said plurality of rows and a plurality of pairs of bit lines each associated with one of said plurality of columns;
- a plurality of sense amplifiers connected to said plurality of pairs of bit lines;
- a refresh-cycle program circuit for programming refresh cycles;
- an address generating circuit for generating refresh address signals for use in refresh operations;
- a self-refresh control circuit for incrementing a value represented by said refresh address signals at predetermined time intervals in self-refresh mode;
- and
- select means for selecting at least one of said plurality of memory blocks in accordance with one of said refresh cycles programmed by said refresh-cycle program circuit, selecting one of said plurality of word lines of each of the at least one selected memory block and activating some of said plurality of sense amplifiers associated with at least one selected memory block.
4 more elements
Dependencies are inferred from the claim text.