Diversity receiver

A diversity receiver comprising:

• a pair of receiving circuits, each receiving a radio signal through an antenna and each outputting receiving data including an error rate and receiving level data indicating an electric field intensity;
• receiving level judge means for judging which one of said receiving circuits is outputting a higher level of said receiving level data, and for selecting and outputting said receiving data of the receiving circuit judged;
• and
• fault detection means for calculating said error rate of said receiving data of each of said receiving circuits, and for detecting a faulty one of said receiving circuits by a result of calculated error rate, and for disconnecting the detected faulty receiving circuit from operation,
• wherein said fault detection means comprises:
• a pair of error rate accumulation circuits, each coupled with a corresponding one of said receiving circuits, for accumulating error rate of said receiving data being output from said receiving circuit;
• a pair of first error rate judge circuits, each coupled with a corresponding error rate accumulation circuit for comparing the accumulated error rate, output from said error rate accumulation circuit, with a predetermined first value, and for outputting a first active signal indicating the accumulated error rate being exceeded by said predetermined first value;
• a first comparing circuits coupled with both of said first error rate judge circuits, for comparing the output signals of the first error rate judge circuits, and for outputting a second active signal when both of the output signals do not coincide with each other;
• a second error rate judge circuit, coupled with both error rate accumulation circuits, for comparing an absolute value of a difference of accumulated error rates, output from said each error rate accumulation circuit, with a predetermined second value, and for outputting a second active signal indicating that the absolute value of the difference of accumulated error rates exceeds said predetermined second value;
• a second comparing circuit coupled with said first comparing circuit and said second error rate judge circuit, for comparing output signals of said first comparing circuit and said second error rate judge circuit, and for outputting a third active signal when said output signals are said first active signal and said second active signal;
• a third error rate judge circuit, coupled with both error rate accumulation circuits for comparing accumulated error rates, output from said each error rate accumulation circuit, with each other, and for outputting a discrimination information indicative of the receiving circuit of said receiving circuits whose accumulated error rate is higher than the accumulated error rate of the other receiving circuit in said pair;
• and
• control means, coupled with said second comparing circuit and said third error rate judge circuit, for detecting output signal of said second comparing circuit, and for disconnecting from operation the receiving circuit indicated by said discrimination information of said third error rate judge circuit when said output signal of said second comparing circuit is said third active signal.