DRAM cell with a roughened poly-Si electrode

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:

• forming a double polysilicon layer on a substrate, said double polysilicon layer comprises a first sublayer and a second sublayer on said first sublayer, wherein the dosage of said first sublayer is about 4E15-1E16 atoms/cm.sup.2, and the dopant is phosphorous said first sublayer is activated at a temperature about 600-1000.degree. C., the dosage of said second sublayer is about 4E15-1.2E16 atoms/cm.sup.2, and the dopant is phosphorous, said second sublayer is activated at a temperature about 600-1000.degree. C.;
• etching said double polysilicon layer to form a porous silicon layer by using hot phosphoric acid at a temperature about 60-165.degree. C. for about 3-200 minutes, the concentration of said hot phosphoric acid is about 30-90%;
• etching said porous layer to form a roughened polysilicon layer by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes, said SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, the volume ratio for the three compounds of said SC-1 is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20;
• forming a dielectric film on said roughened polysilicon layer;
• forming a conductive layer over said dielectric film;
• and
• etching said conductive layer, said dielectric film and said roughened polysilicon layer.

A method of forming a roughened polysilicon electrode comprising the steps of:

• forming a polysilicon layer on a substrate;
• etching said polysilicon layer to form a porous silicon layer by using hot phosphoric acid at a temperature at least about 60.degree. C. but less than 150.degree. C. for about 3-200 minutes, the concentration of said hot phosphoric acid is about 30-90%;
• and
• etching said porous layer to form a roughened polysilicon layer by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes, said SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, wherein the volume ratio for the three compounds of said SC-1 layer is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20.

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of:

• forming a polysilicon layer on a substrate;
• etching said polysilicon layer to form a porous silicon layer by using hot phosphoric acid;
• etching said porous layer with (H.sub.2 SO.sub.4 +H.sub.2 O.sub.2), (NH.sub.4 OH+H.sub.2 O.sub.2 +H.sub.2 O) and (HCl+H.sub.2 O.sub.2 +H.sub.2 O), in any order, to form a roughened polysilicon layer;
• forming a dielectric film on said roughened polysilicon layer;
• forming a conductive layer over said dielectric film, and
• etching said conductive layers, said dielectric film and said roughened polysilicon layer.