Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion

A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

• forming a gate electrode and a gate oxide over a semiconductor substrate;
• implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide, wherein the step of implanting the region where the drain is formed with the large tilt angle implant comprises implanting a sub-amorphous dose into the drain region;
• forming a lightly doped drain extension region in the region of the substrate where the drain is formed;
• forming a drain in the region where the drain is formed and a source in a source region of the substrate;
• and
• thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.

A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

• forming a gate electrode and a gate oxide over a semiconductor substrate;
• implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide, wherein a dose of the large tilt angle implant is about 10-30 percent of an amorphizing dose;
• forming a lightly doped drain extension region in the region of the substrate where the drain is formed;
• forming a drain in the region where the drain is formed and a source in a source region of the substrate;
• and
• thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.

A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

• forming a gate electrode and a gate oxide over a semiconductor substrate;
• implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide;
• forming a lightly doped drain extension region in the region of the substrate where the drain is formed;
• forming a drain in the region where the drain is formed and a source in a source region of the substrate;
• and
• thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region,
• further comprising the step of forming a first sidewall spacer on a drain side of the gate and the gate oxide before the implanting of the region where the drain is formed with the large tilt angle implant, wherein a thickness of the first sidewall spacer controls the location of dopants under the gate oxide, thereby allowing the reduce channel length of the transistor to be customized.

A method of forming a transistor, comprising the steps of:

• forming a gate electrode and a gate oxide over a semiconductor substrate;
• supplying interstitials in at least one of a region of the substrate where a drain is formed and a region of the substrate where a source is formed;
• forming an extension region in the at least one of the region where the drain is formed and the region where the source is formed;
• forming a drain in the region where the drain is formed and a source in a region where the source is formed;
• and
• thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the extension region.