US 5,970,351 A · Production method for a MISFET, complementary MISFET

Abstract

A method of producing a transistor having a source and drain diffusion layer formed so that is has a junction of a shallow depth and is low in parasitic resistance and parasitic capacitance. The method allows the manufacture of a transistor having a gate insulator formed on a principal plane of a semiconductor substrate, a gate electrode formed on the gate insulator, and source and drain diffusion layers of one conductivity type formed on the principal plane of the semiconductor substrate across the gate electrode. A semiconductor thin film layer doped with an impurity of the same conductivity type is selectively deposited on the principal plane of the semiconductor substrate on which the source and drain diffusion layers are formed. A facet face is formed at an end portion of the semiconductor thin film which opposes to a sidewall of the gate electrode. The facet face has an inclination angle between a sidewall face of the gate electrode and the principal plane of the semiconductor substrate.

Claims20

Dependent claims

A method of producing an MISFET, said method comprising:

forming a gate electrode on a gate insulator on a principal plane of a semiconductor substrate;
forming a first insulator on a sidewall face of said gate electrode;
selectively forming a uniformly doped semiconductor thin film layer containing an impurity of one conductivity type in a region of said principal plane of said semiconductor substrate for subsequent use in forming a source and drain diffusion layer;
and
forming a facet at an end portion of said semiconductor thin film next to said first insulator on said sidewall face of said gate electrode, said facet having an inclination angle between said sidewall face of said gate electrode and said principal plane of said semiconductor substrate.

2 more elements

A method of producing a complementary MISFET device comprising both n-type and p-type MISFETS, said method comprising:

forming a gate electrode on a gate insulator on a principal plane of a semiconductor substrate;
forming a first insulator on a sidewall face of said gate electrode;
selectively forming a uniformly doped first semiconductor thin film layer containing an impurity of one conductivity type in a region of said principal plane of said semiconductor substrate for subsequent use in forming a source and drain diffusion layer;
and
forming a facet at an end portion of said first semiconductor thin film next to said first insulator on said sidewall face of said gate electrode, said facet having an inclination angle between said sidewall face of said gate electrode and said principal plane of said semiconductor substrate, thereby forming said complementary MISFET.

2 more elements

Dependencies are inferred from the claim text.

Production method for a MISFET, complementary MISFET

Life of this patent

Production method for a MISFET, complementary MISFET

Life of this patent

Abstract

Claims20