High performance mosfet transistor fabrication technique
AssigneeAdvanced Micro Devices, Inc.
InventorsMark I. Gardner, H. Jim Fulford, Jr.
Life of this patent
Estimating the term…
Abstract
A semiconductor fabrication process in which nitrogen is incorporated into the transistor gate without significantly increasing the resistivity of the source/drain region. The incorporation of nitrogen into the gate structure substantially reduces the migration of impurity dopants from the silicon gate into the transistor channel region resulting in a more stable and reliable transistor. In one embodiment, a tail of the nitrogen impurity distribution incorporated into the gate structure extends into the channel region of the semiconductor substrate. In this embodiment, the nitrogen within the channel region prevents excessive lateral diffusion of source/drain impurities thereby permitting the fabrication of deep sub-micron transistors.
Claims14
A semiconductor process comprising:
- providing a semiconductor substrate;
- forming a gate dielectric layer on an upper surface of said semiconductor substrate;
- depositing a conductive layer on an upper surface of said gate dielectric layer;
- implanting a nitrogen bearing impurity distribution into said conductive layer, wherein said implanting of said nitrogen bearing impurity distribution is accomplished such that a peak impurity concentration of said nitrogen bearing impurity distribution is located at or above a midpoint in said conductive gate layer, and wherein a lower tail of said nitrogen bearing impurity distribution is located within said conductive gate layer whereby said nitrogen bearing impurity distribution is substantially prevented from entering said semiconductor substrate;
- subsequent to said implanting a nitrogen bearing impurity distribution, patterning said conductive layer to produce a conductive gate structure, wherein said conductive gate structure is aligned over a channel region of said semiconductor substrate;
- and
- simultaneously implanting a first source/drain impurity distribution into said semiconductor substrate wherein said conductive gate structure acts as an implant mask during said implanting whereby said first impurity distribution is laterally disposed on either side of said channel region.
A semiconductor process comprising:
- providing a semiconductor substrate;
- forming a gate dielectric layer on an upper surface of said semiconductor substrate;
- depositing a conductive layer on an upper surface of said gate dielectric layer;
- implanting a nitrogen bearing impurity distribution into said conductive layer;
- patterning said conductive layer to produce a conductive gate structure, wherein said conductive gate structure is aligned over a channel region of said semiconductor substrate;
- simultaneously implanting a first source/drain impurity distribution into said semiconductor substrate wherein said conductive gate structure acts as an implant mask during said implanting whereby said first source/drain impurity distribution is laterally disposed on either side of said channel region;
- forming a drain mask over an LDD region and a drain region of said semiconductor substrate, wherein said LDD region is part of said first source/drain impurity distribution, and wherein said LDD region is laterally disposed between said drain region and said channel region of said semiconductor substrate;
- subsequent to said implanting a first source/drain impurity distribution, implanting a source impurity distribution into said semiconductor substrate wherein said source impurity distribution is aligned with said conductive gate structure and further whereby said source impurity distribution is substantially excluded from said channel region, said LDD region, and said drain region of said semiconductor substrate;
- removing said drain mask from said semiconductor substrate;
- forming spacer structures on respective sidewalls of said conductive gate structure, wherein said spacer structures mask a region of said semiconductor substrate upper surface proximal to said channel region including said LDD region;
- and
- implanting a drain impurity distribution into said semiconductor substrate, wherein said conductive gate structure and said spacer structures mask said drain impurity distribution whereby said drain impurity distribution is substantially excluded from said channel region and said LDD region.
Dependencies are inferred from the claim text.