US 5,970,343 AGranted

Fabrication of conductivity enhanced MOS-gated semiconductor devices

AssigneeHarris Corporation

InventorChristopher Boguslaw Kocon

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Abstract

In the manufacture of an MOS gated semiconductor device, indentations are provided on a surface of a semiconductor wafer extending inwardly of respective spaced apart regions at the wafer surface having doping concentrations greater than that present in the remainder of the wafer. A layer of silicon having a doping concentration less than that of the substrate is conformally provided on the substrate surface whereby the indentations in the substrate surface are replicated on the surface of the silicon layer. Dopants in the substrate regions are then out-diffused into the silicon layer to provide highly doped buried regions within the layer. Then, using the silicon layer surface indentations as photomask alignment marks, gate electrode structures are formed on and within the silicon layer in preselected orientation relative to the buried regions. The buried regions provide low resistance paths for current through the resulting devices.

Claims5

Dependent claims

A method of fabricating an MOS gated semiconductor device comprising the steps of:

providing, at a surface (214) on a first side of a silicon substrate (224a) having a first concentration of a first conductivity (N) type of dopants therein, a first region (217) having a second concentration of first conductivity type dopants higher than said first concentration, forming a first indentation (217a) in a surface (214a) on said first side of said silicon substrate extending into said first region, depositing a layer 224 of silicon having a third concentration of first conductivity type dopants less than said first concentration on said first side of said silicon substrate and into said first indentation for replicating said first indentation as a second indentation (217b) on a surface of said silicon layer, out-diffusing dopants from said first region into said silicon layer for forming a buried region (217c) in said silicon layer extending towards said second indentation (217b), and forming a gate electrode structure (212) on said silicon layer surface in spatial relation with said buried region.

Dependencies are inferred from the claim text.