Method of forming high capacitive-coupling ratio and high speed flash memories with a textured tunnel oxide

A method for manufacturing a nonvolatile memory on a semiconductor substrate, said method comprising the steps of:

• forming a gate oxide layer on said semiconductor substrate;
• forming a first polysilicon layer on said gate oxide;
• forming a silicon nitride layer on said first polysilicon layer;
• patterning said silicon nitride layer, said first polysilicon layer and said gate oxide layer to form a gate structure on said semiconductor substrate;
• performed a first thermal oxidation to form a first oxide layer on said semiconductor substrate exposed by said gate structure and simultaneously form a polyoxide on side walls of said gate structure;
• forming silicon nitride spacers on side walls of said gate structure;
• performing an ion implantation to form source and drain of said nonvolatile memory in said semiconductor substrate;
• performing a second thermal oxidation to form a second oxide layer on said semiconductor substrate exposed by said gate structure and said silicon nitride spacers, wherein the dopants of said first ion implantation being driven into said semiconductor substrate;
• removing said silicon nitride layer, said silicon nitride spacers, then removing said polyoxide layer and said gate oxide that is uncovered by said gate structure;
• forming undoped amorphous silicon layer along a surface of said gate structure and said second oxide layer;
• performing a third thermal oxidation by dry oxidation process in O.sub.2 ambient at about 700 to 1000 degrees centigrade to convert said undoped amorphous silicon layer into a third oxide layer having textured interface between said semiconductor substrate and said third oxide layer;
• forming a second polysilicon layer on said third oxide layer;
• anisotropically etching said second polysilicon layer, thereby forming polysilicon side wall spacers on said side walls of said gate structure, said third oxide layer at top of said gate structure and uncovered by said polysilicon side wall spacers being removed, said third oxide layer remaining under said polysilicon side wall spacers being used as a tunneling oxide;
• forming a third polysilicon layer on said gate structure, said polysilicon side wall spacers;
• patterning said third polysilicon layer to define a floating gate region, said first polysilicon layer, said polysilicon side wall spacers and said third polysilicon layer to being used as a floating gate;
• forming an inter poly dielectric layer on said floating gate;
• and
• forming a forth polysilicon layer on said inter poly dielectric layer, wherein said forth polysilicon layer is used as a control gate.