Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate

A semiconductor processing method of forming CMOS static random access memory within a semiconductor substrate, the method comprising the following steps:

• forming first, second, third and fourth field effect transistor gates on a substrate, the first and second gates to be utilized for formation of cross-coupled SRAM n-type field effect driver transistors, the third and fourth gates to be utilized for formation of SRAM p-type field effect load transistors, the first and second gates defining respective opposing substrate regions for formation of desired opposing n-type substrate active regions, the third and fourth gates defining respective opposing substrate regions for formation of desired opposing p-type substrate active regions;
• forming an insulating layer over the substrate over the desired n-type regions and the p-type doped regions;
• forming voids through the insulating layer to the desired n-type regions;
• filling the voids with n-type conductively doped polysilicon plugs, the plugs having an n-type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3, the desired n-type regions having an n-type dopant concentration prior to the filling step which is in the range of from 0 ions/cm.sup.3 to 1.times.10.sup.19 ions/cm.sup.3 ;
• out-diffusing n-type dopant impurity from the n-type conductively doped polysilicon plugs into the substrate to form the desired n-type active regions having an n-type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3 in the substrate;
• electrically interconnecting one of the conductive plugs of the first driver transistor to one of the conductive plugs of the second driver transistor;
• electrically interconnecting the other conductive plug of the first driver transistor with the second gate and with one of the p-type regions of one of the load transistors;
• and
• electrically interconnecting the other conductive plug of the second driver transistor with the first gate and with one of the p-type regions of the other load transistor.

A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate, the method comprising the following steps:

• defining first and second portions of a substrate;
• forming a masking layer over the first portion of the substrate;
• with the masking layer over the first portion of the substrate, implanting a second conductivity type dopant into the second portion of the substrate;
• removing the masking layer;
• forming an insulating layer over the first and second portions of the substrate;
• forming a void through the substrate to the first portion;
• filling the void with a first conductivity type doped polysilicon plug;
• and
• out-diffusing first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the first portion of the substrate to form a first conductivity type active region within the first portion of the substrate.

A method of forming an n-type field effect transistor, p-type field effect transistor complementary to the n-type field effect transistor, and at least one memory transistor comprising the following steps:

• forming a first transistor gate, a second transistor gate, and a third transistor gate over a substrate;
• the first, second and third transistor gates ultimately comprising transistor gates for an n-type field effect transistor, a p-type field effect transistor complementary to the n-type field effect transistor, and a memory transistor, respectively;
• forming n-type LDD regions adjacent the first and third transistor gates;
• forming p-type source and drain regions adjacent the second transistor gate;
• forming an insulative layer over the substrate;
• forming plugs extending through the insulative layer to the substrate proximate the first and third transistor gates;
• forming n-type source and drain regions beneath the plugs and adjacent the first and third transistor gates;
• and
• wherein no more than two masking steps occur after forming of the first, second and third transistor gates through formation of all 1) said n-type source and drain regions, 2) said n-type LDD regions, 3) said p-type source and drain regions, and 4) said polysilicon plugs.

A method of forming an n-type field effect transistor, p-type field effect transistor complementary to the n-type field effect transistor, and at least one memory transistor comprising the following steps:

• forming a first transistor gate, a second transistor gate, and a third transistor gate over a substrate;
• the first, second and third transistor gates ultimately comprising transistor gates for an n-type field effect transistor, a p-type field effect transistor complementary to the n-type field effect transistor, and a memory transistor, respectively;
• forming n-type LDD regions adjacent the first and third transistor gates;
• forming n-type source and drain regions adjacent the first and third transistor gates;
• forming p-type source and drain regions adjacent the second transistor gate;
• and
• wherein no more than two masking steps occur after forming the first, second and third transistor gates through formation of all 1) said n-type source and drain regions, 2) said n-type LDD regions, and 3) said p-type source and drain regions.