Method of making field effect transistor with higher mobility
AssigneeAdvanced Micro Services, Inc.
InventorMatthew S. Buynoski
Life of this patent
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Abstract
A method of increasing the performance of an FET device by aligning the channel of the FET with the [110] crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45.degree. relative to each other so that, instead of the channel being aligned parallel with the [100] crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the [110] crystal direction. The mobility of the carriers is higher in the [110] crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the [110] crystal direction.
Claims20
A method of forming a field effect transistor (FET), having a source, drain and gate with the source and drain separated by a channel when voltage is applied to the gate, by a number of fabricating steps, including an exposure step, comprising:
- positioning a {100} monocrystalline silicon wafer having a [100] crystal direction for exposing the wafer to images for fabricating at least one FET;
- exposing said {100} wafer with the relationship of said wafer and said images being 45.degree. from the [100] crystal direction and in a [110] crystal direction of said wafer;
- and
- performing non-exposure fabricating steps with said {100} wafer positioned in the [100] crystal direction, whereby the channel of the fabricated FET is aligned approximately parallel with the [110] crystal direction of said {100} wafer.
A method of fabricating a field effect transistor (FET) comprising the steps of:
- positioning a {100} monocrystalline silicon wafer having (100) and (110) crystal planes and [100] and [110] crystal directions for exposing the wafer to images for fabricating at a FET;
- exposing said {100} wafer with the relationship of said wafer and said images being 45.degree. from the [100] crystal direction and in the [110] crystal direction of said wafer to create a gate pattern having a gate width aligned in the [110] crystal direction;
- positioning the {100} wafer in the [100] crystal direction for performing at least one non-exposure step in the [100] crystal direction;
- and
- completing the fabricating of the FET with a source and a drain and the gate with the source and drain separated by the gate width and a channel under the gate, whereby the channel of the fabricated FET is aligned approximately parallel with the [110] crystal direction of said {100} wafer.
In a method of fabricating an integrated circuit with at least one field effect transistor (FET) comprising the steps of:
- positioning a {100} monocrystalline silicon substrate having (100) and (110) crystal planes and [100] and [110] crystal directions for exposing the wafer to images for fabricating at least one FET;
- thermally growing a silicon oxide layer in the silicon substrate and aligned with the [100] crystal direction;
- creating a gate pattern having a gate width in the [110] crystal direction so that the gate width is aligned approximately orthogonal to the (110) crystal plane and parallel with the [110] crystal direction;
- forming a source on one side of gate width and a drain on the other side of the gate width;
- and
- creating a channel under the gate between the source and drain aligned in a direction parallel with the [110] crystal direction of the gate width, whereby the performance of the FET is enhanced due to a higher mobility of the carriers in the [110] crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the substrate by being disposed in the [100] crystal direction.
Dependencies are inferred from the claim text.