Method of fabricating a microelectronic package having polymer ESD protection
AssigneeLSI Logic Corporation
InventorJames W. Hively
Life of this patent
Estimating the term…
Loading patent…
AssigneeLSI Logic Corporation
InventorJames W. Hively
Estimating the term…
A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX.TM., which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.
A method of fabricating a semiconductor device, comprising the steps of:
A method of fabricating a microelectronic package, comprising the steps of:
A method of fabricating a microelectronic package, comprising the steps of:
A method of fabricating a microelectronic package, comprising the steps of:
A method of fabricating a microelectronic package, comprising the steps of:
Dependencies are inferred from the claim text.