Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing system

A data processing system, comprising:

• a microprocessor having an instruction execution pipeline;
• a subsystem connected to the microprocessor having a data pipeline;
• circuitry for executing system code in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of operations in the instruction execution pipeline and in the data pipeline;
• circuitry for sending a first signal from the processor to the subsystem to indicate a pending halt;
• circuitry for conditioning the subsystem for halting in response to receipt of the first signal;
• circuitry for halting the normal operation of the processor pipeline such that at least one of the plurality of operations is still pending;
• circuitry for sending a second signal to the subsystem to indicate the processor pipeline is halted;
• circuitry for halting the subsystem in response to receipt of the second signal such that any of the operations in the subsystem pipeline which correspond to the at least one of the plurality of operations still pending in the instruction execution pipeline is maintained;
• and
• circuitry for resuming execution of the system code in the processor instruction execution pipeline in a manner that no extraneous operations occur within the data processing system.