Device to assist software emulation of hardware functions

A method for software emulation of hardware functions in a computer system, the method comprising the steps of:

• (a) obtaining a first address from a bus, wherein the first address is part of a bus cycle corresponding to a request issued on the bus;
• (b) comparing the first address to a set of one or more addresses;
• (c) asserting an interrupt signal only if both the first address matches an address of the set of one or more addresses and a first indicator is set to indicate an interrupt is to be issued on a next trap hit, the interrupt signal causing a microprocessor, resident within the computer system, to enter a system management mode and initiate the execution of a hardware device emulator;
• and
• (d) terminating the bus cycle upon completion of the emulator.

An apparatus comprising:

• a controller having a plurality of operating modes including a system management mode;
• a decoder to compare a first address to a set of one or more addresses and to provide a first indication which indicates whether the first address is one of the set of one or more addresses, wherein the first address corresponds to a request issued on a bus;
• a second indication which indicates whether to issue an interrupt on a next trap hit;
• and
• a trap logic control, coupled to the decoder and the second indication, to assert an interrupt signal only if both the first indication indicates the first address is one of the set of one or more addresses and the second indication indicates to issue an interrupt on the next trap hit, wherein said controller, in response to the assertion of said interrupt line, enters said system management mode and invokes a hardware device emulator.

An apparatus for assisting software emulation of hardware functions in a computer system, the apparatus comprising:

• means for obtaining a first address from a bus, wherein the first address is part of a bus cycle corresponding to a request issued on the bus;
• means for comparing the first address to a set of one or more addresses;
• means for asserting an interrupt signal only if both the first address matches an address of the set of one or more addresses and a first indicator is set to indicate an interrupt is to be issued on a next trap hit, the interrupt signal causing a controller, resident in the computer system, to enter a system management mode and initiate execution of an emulator;
• and
• means for terminating the bus cycle upon completion of the emulator.

A computer system comprising:

• a bus;
• and
• a mechanism coupled to said bus, said mechanism including:
• a decoder to compare a first address to a set of one or more addresses and to provide a indication which indicates whether the first address is one of the set of one or more addresses, wherein the first address corresponds to a request issued on the bus,
• a second indication which indicates whether to issue an interrupt on a next trap hit, and
• a trap control logic, coupled to the decoder and the second indication, to assert an interrupt signal only if both the first indication indicates the first address is one of the set of one or more addresses and the second indication indicates to issue an interrupt on the next trap hit, wherein said interrupt causes a resident controller to enter a system management mode in which software emulation of a hardware device is invoked.