Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions

An instruction cache for a processor of the type having a variable byte-length instruction format, comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of instruction bytes and a corresponding at least one predecode bit for each of the instruction bytes;
• first means for prefetching a plurality of instruction bytes from an instruction source;
• second means for predecoding each of the prefetched instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched instruction byte;
• third means for storing the plurality of prefetched instruction bytes and corresponding at least one predecode bit for each prefetched instruction byte into an instruction block within the array;
• fourth means for delivering a requested stream of instruction bytes and corresponding at least one predecode bit from an instruction block within the array to an instruction decoder of the processor;
• and
• wherein the at least one predecode bit corresponding to each of the instruction bytes includes a first bit for indicating, when asserted, that the corresponding instruction byte, as prefetched and predecoded, is a starting byte of an instruction.

An instruction cache for a processor of the type having a variable byte-length instruction format, comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of instruction bytes and a corresponding at least one predecode bit for each of the instruction bytes;
• first means for prefetching a plurality of instruction bytes from an instruction source;
• second means for predecoding each of the prefetched instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched instruction byte;
• third means for storing the plurality of prefetched instruction bytes and corresponding at least one predecode bit for each prefetched instruction byte into an instruction block within the array;
• fourth means for delivering a requested stream of instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor;
• and
• wherein the at least one predecode bit corresponding to each of the instruction bytes includes a second bit for indicating, when asserted, that the corresponding instruction byte, as prefetched and predecoded, is an ending byte of an instruction.

An instruction cache for a processor of the type having a variable byte-length instruction format, comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of instruction bytes and a corresponding at least one predecode bit for each of the instruction bytes;
• first means for prefetching a plurality of instruction bytes from an instruction source;
• second means for predecoding each of the prefetched instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched instruction byte;
• third means for storing the plurality of prefetched instruction bytes and corresponding at least one predecode bit for each prefetched instruction byte into an instruction block within the array;
• fourth means for delivering a requested stream of instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor;
• and
• wherein the at least one predecode bit corresponding to each of the instruction bytes includes a bit for indicating, when asserted, that the corresponding instruction byte, as prefetched and predecoded, is an opcode byte of an instruction.

An instruction cache for a processor of the type having a variable byte-length instruction format, comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of instruction bytes and a corresponding at least one predecode bit for each of the instruction bytes;
• first means for prefetching a plurality of instruction bytes from an instruction source;
• second means for predecoding each of the prefetched instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched instruction byte;
• third means for storing the plurality of prefetched instruction bytes and corresponding at least one predecode bit for each prefetched instruction byte into an instruction block within the array;
• fourth means for delivering a requested stream of instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor;
• and
• wherein the at least one predecode bit corresponding to each of the instruction bytes includes a group of bits for identifying an instruction byte according to which instruction fields, as prefetched and predecoded, are provided by the corresponding instruction byte.

In a super-scalar CISC processor of the type having a variable byte-length instruction format wherein each CISC instruction is mapped to a corresponding sequence of one or more internal RISC-type instructions for execution within a superscalar RISC-type core processor, an instruction cache comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of CISC instruction bytes and a corresponding at least one predecode bit for each of the CISC instruction bytes;
• first means for prefetching a plurality of CISC instruction bytes from an instruction source;
• second means for predecoding each of the prefetched CISC instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched CISC instruction byte;
• third means for storing the plurality of prefetched CISC instruction bytes and corresponding at least one predecode bit for each prefetched CISC instruction byte into an instruction block within the array;
• and
• fourth means for delivering a requested stream of CISC instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor.

A method for an instruction cache for a processor of the type having a variable byte-length instruction format, the method comprising:

• storing a plurality of instruction blocks in an array, each of the instruction blocks comprising a plurality of instruction bytes and a corresponding at least one predecode bit for each of the instruction bytes;
• prefetching a plurality of instruction bytes from an instruction source;
• predecoding each of the prefetched instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched instruction byte;
• storing the plurality of prefetched instruction bytes and corresponding at least one predecode bit for each prefetched instruction byte into an instruction block within the array;
• and
• delivering a requested stream of instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor.

In a super-scalar CISC processor of the type having a variable byte-length instruction format wherein each CISC instruction is mapped to a corresponding sequence of one or more internal RISC-type instructions for execution within a superscalar RISC-type core processor, a method for an instruction cache, the method comprising:

• storing a plurality of instruction blocks in an array, each of the instruction blocks comprising a plurality of CISC instruction bytes and a corresponding at least one predecode bit for each of the CISC instruction bytes;
• prefetching a plurality of CISC instruction bytes from an instruction source;
• predecoding each of the prefetched CISC instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched CISC instruction byte;
• storing the plurality of prefetched CISC instruction bytes and corresponding at least one predecode bit for each prefetched CISC instruction byte into an instruction block within the array;
• and
• delivering a requested stream of CISC instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor.

An instruction cache for a processor of the type having a variable byte-length instruction format, comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of instruction bytes and a corresponding at least one predecode bit for each of the instruction bytes;
• an interface unit that prefetches a plurality of instruction bytes from an instruction source;
• a predecoder that predecodes each of the prefetched instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched instruction byte;
• a cache that stores the plurality of prefetched instruction bytes and the corresponding at least one predecode bit for each prefetched instruction byte into an instruction block within the array;
• and
• a queue that delivers a requested stream of instruction bytes and the corresponding at least one predecode bit from an instruction block within the array to an instruction decoder of the processor.

In a super-scalar CISC processor of the type having a variable byte-length instruction format wherein each CISC instruction is mapped to a corresponding sequence of one or more internal RISC-type instructions for execution within a superscalar RISC-type core processor, an instruction cache comprising:

• an array for storing a plurality of instruction blocks, each of the instruction blocks comprising a plurality of CISC instruction bytes and a corresponding least one predecode bit for each of the CISC instruction bytes;
• an interface means for prefetching a plurality of CISC instruction bytes from an instruction source;
• a predecoder that predecodes each of the prefetched CISC instruction bytes to determine each of the corresponding at least one predecode bit for each prefetched CISC instruction byte;
• a cache that stores the plurality of prefetched CISC instruction bytes and corresponding at least one predecode bit for each prefetched CISC instruction byte into an instruction block within the array;
• and
• a queue that delivers a requested stream of CISC instruction bytes and corresponding predecode bits from an instruction block within the array to an instruction decoder of the processor.