Precise, low-jitter fractional divider using counter of rotating clock phases

A phase-locked loop comprising:

• an input clock having an input frequency;
• a phase comparator coupled to the input clock and to a feedback clock, the phase comparator comparing the input clock to the feedback clock and generating a control voltage in response to a difference between the input clock and the feedback clock;
• a voltage-controlled oscillator (VCO), coupled to the control voltage from the phase comparator, for generating an output clock having an output frequency determined by the control voltage;
• and
• a fractional divider, receiving the output clock, for generating the feedback clock, the fractional divider generating the feedback clock with a frequency equal to the output frequency divided by M.N, where M is an integer part and N is a fractional part of a non-whole number,
• wherein the VCO includes means for generating a plurality of multi-phase clocks, the fractional divider further comprises:
• a phase mux, receiving the plurality of multi-phase clocks from the VCO, the plurality of multi-phase clocks having equally-spaced phase differences within a period of the output clock, the phase mux for outputting a selected clock;
• a state machine, coupled to control the phase mux, for sequencing through a plurality of N states, each new state controlling the phase mux to select a multi-phase clock having a larger phase delay;
• a counter, coupled to the selected clock, for counting M pulses of the selected clock and then outputting an end of a period of the feedback clock,
• wherein a first N periods of the selected clock are longer in duration than a last M-N states of the selected clock, wherein the frequency of the feedback clock is M.N times the output frequency.

A method for dividing an input clock by a non-whole number divisor M.N, the divisor having an integer part M and a decimal part N, the method comprising the steps of:

• generating a plurality of multi-phase clocks from the input clock, the multi-phase clocks having equally-spaced phase shifts over a period of the input clock;
• selecting one of the multi-phase clocks as a selected clock;
• rotating a state machine in a first direction to a next state, and selecting as the selected clock another of the multi-phase clocks having a next-larger phase shift to the selected clock in response to an edge of the selected clock;
• wherein a period of the selected clock is larger than a period of the input clock by the phase shift when the state machine is rotated;
• incrementing a counter in response to the edge of the selected clock;
• continuing to rotate the state machine and select another multi-phase clock having larger phase shifts for a first N cycles of the selected clock;
• halting rotation of the state machine and selecting a same multi-phase clock after N cycles of the selected clock;
• wherein the period of the selected clock is equal to the period of the input clock when the state machine is not rotated;
• continuing to increment the counter for M cycles of the selected clock;
• and
• generating an output from the counter after M cycles of the selected clock, the output having a frequency equal to the input clock's frequency divided by M.N,
• whereby M.N periods of the input clock before the output from the counter is generated.