US 5,970,097 A · Arithmetic apparatus for use in Viterbi decoding

Abstract

An arithmetic apparatus comprising a memory 1 for storing path select signals, a barrel shifter 3 for shifting data read from the memory, a shift register 4 for receiving a bit shifted to a MSB by the barrel shifter and means 5 for generating the number of shifts which are performed by the barrel shifter by converting data positioned at a specific bit position in the shift register, wherein path select signals at the same time are divided into a plurality of groups, and then stored in the memory, and the arithmetic apparatus includes address generating means 10 for outputting the address, and address conversion means 7 for generating the address of the group which must be read by combining the address and a value of a specific bit position in the shift register with each other. Thus, tracing back in Viterbi decoding can be performed with a short bit width.

Claims15

Dependent claims

An arithmetic apparatus comprising:

a data memory for storing path select signals in a manner that path select signals at the same time are divided into a plurality of groups;
a barrel shifter for shifting data read from said data memory;
a shift register for receiving one bit shifted to a MSB by said barrel shifter;
data conversion means for generating the number of shifts which are performed by said barrel shifter by converting data positioned at a specific bit position in said shift register so as to perform Viterbi decoding process for generating the number of shifts which are performed by said barrel shifter;
address generating means for outputting the address in said data memory;
and
address conversion means for generating the address of said group, which is read from said data memory, in accordance with the address output from said address generating means and the value of a specific bit position in said shift register.

4 more elements

A radio station apparatus comprising:

an antenna portion for receiving and transmitting a signal;
a radio portion including a receiving portion for receiving a receiving signal from said antenna portion, and a transmitting portion for transmitting a transmission signal to said antenna portion;
a base-band signal processing portion including a demodulation portion which demodulate the receiving signal from said receiving portion, a modulation portion which modulates the transmission signal, and a digital signal processor which performs the encoding and decoding;
a control portion for controls said antenna portion, said radio portion, said base-band signal processing portion;
and
an input-output portion for inputting and outputting the signals from and to an external;
wherein said base-band signal processing portion includes an arithmetic apparatus comprising:
a data memory for storing path select signals in a manner that path select signals at the same time are divided into a plurality of groups;
a barrel shifter for shifting data read from said data memory;
a shift register for receiving one bit shifted to a MSB by said barrel shifter;
data conversion means for generating the number of shifts which are performed by said barrel shifter by converting data positioned at a specific bit position in said shift register so as to perform Viterbi decoding process for generating the number of shifts which are performed by said barrel shifter;
address generating means for outputting the address in said data memory;
and
address conversion means for generating the address of said group, which is read from said data memory, in accordance with the address output from said address generating means and the value of a specific bit position in said shift register.

11 more elements

Dependencies are inferred from the claim text.

Arithmetic apparatus for use in Viterbi decoding

Life of this patent

Arithmetic apparatus for use in Viterbi decoding

Life of this patent

Abstract

Claims15