Test pattern generator circuit for IC testing equipment
AssigneeAdvantest Corporation
InventorsNoriyuki Masuda, Shinichi Hashimoto
Life of this patent
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Abstract
Pattern data comprising N=8 words, where one word comprises m=3 bits, delivered in parallel from a pattern memory 2 is input to a parallel/serial conversion circuit 3. The circuit 3 can be switched between a serial output mode (MC="0") in which data for one word per pin is serially delivered every test cycle and a parallel-serial output mode in which parallel data for n-2 words per pin (m.times.n bits) are serially delivered every test cycle in response to a mode control signal MC.
Claims8
A test pattern generator circuit for each testing channel of an IC testing equipment in which a test pattern is applied to an IC under test and a response output therefrom is compared against expected value data to detect any fault, comprising
- a pattern memory for delivering pattern data for N words in parallel;
- and a parallel/serial conversion circuit to which N words of the pattern data which are delivered in parallel are fed from the pattern memory and which can be switched between an serial output mode in which data for one word per pin is serially delivered every test cycle and a parallel-serial output mode in which m.times.n bits in the parallel data for n words per pin are serially delivered every test cycle in response to a mode control signal, where one word comprises m bits and N, m and n are integers equal to or greater than two.
Dependencies are inferred from the claim text.