Semiconductor memory device with reduced read disturbance

A method for use in a semiconductor memory device including a memory array with a plurality of wordlines and a plurality of bitlines, the method comprising the steps of:

• supplying select signals to the memory array to select a particular wordline;
• detecting the presence of a transition in at least one of the select signals;
• and
• generating, in response to the transition, a first timing signal indicating a first period of time following the transition after which data read from a selected wordline may be latched, wherein the first period of time is selected as greater than or equal to the sum of:
• (i) a time from the transition until a wordline is selected, and (ii) a data sensing time for memory cells of the selected wordline, and a second timing signal indicating a second period of time following the first period of time after which the previously-selected particular wordline may be deselected at a predetermined time after the transition, wherein the predetermined time corresponds to the sum of the first and second time periods.

A semiconductor memory device comprising:

• a memory array with a plurality of wordlines and a plurality of bitlines;
• a decoder for supplying select signals to the memory array to select a particular wordline;
• a detector for detecting the presence of a transition in at least one of the select signals;
• and
• a timing circuit having an input coupled to an output of the detector, the timing circuit supplying a timing signal to the decoder which directs the decoder to deselect the previously-selected particular wordline at a predetermined time after said transition.