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US 5,970,021 AGranted
Synchronous semiconductor memory device having function of inhibiting output of invalid data
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMikio Sakurai
Life of this patent
Estimating the term…
Abstract
A reset signal generation circuit included in an output control circuit ANDs a reset signal for resetting complementary data buses for transferring data to a second output stage at prescribed timing and an internal control signal corresponding to a read mask signal and outputs a reset signal for resetting other complementary data buses for transferring the data to a final output stage. Thus, invalid data is reset on the complementary data buses.
Claims14
A synchronous semiconductor memory device comprising:
- a plurality of banks each including a memory cell array including a plurality of memory cells being arranged in rows and columns and a plurality of word lines being provided in correspondence to said rows of said memory cell array respectively;
- an internal clock generation circuit for outputting an internal clock signal being synchronized with an external clock signal;
- a read circuit for reading data from any said memory cell of corresponding said bank in synchronization with said internal clock signal in response to a read instruction being inputted from the exterior;
- a data bus for transferring said data being read by said read circuit;
- an output circuit for receiving said data being transferred from said data bus and outputting a signal corresponding to said data to a data output terminal;
- a reset circuit for resetting said data bus;
- and
- an output control circuit for controlling timing for resetting said data bus by said reset circuit,
- said output control circuit bringing said data bus into a reset state in response to a mask signal for inhibiting external output of said data being outputted from said read circuit at prescribed timing.
6 more elements
A synchronous semiconductor memory device comprising:
- a plurality of banks each including a memory cell array including a plurality of memory cells being arranged in rows and columns and a plurality of word lines being provided in correspondence to said rows of said memory cell array respectively;
- an internal clock generation circuit for outputting an internal clock signal being synchronized with an external clock signal;
- a read circuit for reading data from any said memory cell of corresponding said bank in synchronization with said internal clock signal in response to a read instruction being inputted from the exterior;
- a data bus for transferring said data being read by said read circuit;
- an output circuit for receiving said data being transferred from said data bus and outputting a signal corresponding to said data to a data output terminal;
- and
- an output control circuit for controlling transfer of said data from said read circuit to said data bus,
- said output control circuit inhibiting said transfer of said data from said read circuit to said data bus in response to a mask signal for inhibiting external output of said data being outputted from said read circuit at prescribed timing.
5 more elements
A synchronous semiconductor memory device comprising:
- a plurality of banks each including a memory cell array including a plurality of memory cells being arranged in rows and columns and a plurality of word lines being provided in correspondence to said rows of said memory cell array respectively;
- an internal clock generation circuit for outputting an internal clock signal being synchronized with an external clock signal;
- a read circuit for reading data from any said memory cell of corresponding said bank in synchronization with said internal clock signal in response to a read instruction being inputted from the exterior;
- a data bus for transferring said data being read by said read circuit;
- an output circuit including a gate for fetching said data being transferred from said data bus and a buffer for receiving an output of said gate and outputting a signal corresponding to said data to a data output terminal;
- and
- an output control circuit for controlling timing for fetching said data by said gate,
- said output control circuit inhibiting said gate from fetching said data from said data bus in response to a mask signal for inhibiting external output of said data being outputted from said read circuit at prescribed timing.
5 more elements
Dependencies are inferred from the claim text.