Semiconductor memory device with row access in selected column block
AssigneeFujitsu Limited
InventorsTakaaki Suzuki, Shinya Fujioka
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Abstract
A semiconductor memory device which employs a hierarchical word-decode scheme for word selection includes sub-word lines provided for each of column blocks, a control circuit selecting one of the column blocks corresponding to a currently accessed column address in a first case where a currently accessed row address is different from a successively accessed row address, and selecting all of the column blocks in a second case where the currently accessed row address is the same as the successively accessed row address, and a sub-word decoder selectively activating the sub-word lines with respect to all of one or more column blocks selected by the control circuit.
Claims9
A semiconductor memory device which employs a hierarchical word-decode scheme for word selection, said semiconductor memory device comprising:
- sub-word lines provided for each of column blocks;
- a control circuit selecting one of said column blocks corresponding to a currently accessed column address in a first case where a currently accessed row address is different from a successively accessed row address, and selecting all of said column blocks in a second case where said currently accessed row address is the same as said successively accessed row address;
- and
- a sub-word decoder selectively activating said sub-word lines with respect to all of one or more column blocks selected by said control circuit.
A semiconductor memory device which employs a hierarchical word-decode scheme for word selection, said semiconductor memory device comprising:
- a plurality of main-word lines;
- a first reset circuit performing a reset operation resetting a selected one of said main-word lines a predetermined time period after said selected one of said main-word lines is activated;
- sub-word lines provided for each of column blocks;
- a column-block-selection circuit selecting one of said column blocks corresponding to a currently accessed column address so as to selectively activate said sub-word lines with respect to said one of said column blocks;
- and
- a control circuit controlling said first reset circuit to perform the reset operation in a first case where a currently accessed row address is different from a successively accessed row address, and controlling said first reset circuit not to perform the reset operation in a second case where said currently accessed row address is the same as said successively accessed row address.
Dependencies are inferred from the claim text.