Semiconductor integrated circuit and decode circuit for memory

A semiconductor integrated circuit comprising plural circuit blocks each including:

• plural logic circuits each having the same configuration and including plural transistors;
• and
• a switching circuit for connecting said plural logic circuits with a predetermined power supply,
• wherein said switching circuit includes a single merged transistor formed by merging a part of transistors having the same function of said plural logic circuits, and
• said merged transistor of said switching circuit has a threshold voltage higher than a threshold voltage of another transistor included in each of said logic circuits, and receives, at a gate thereof, a block selecting signal for selecting one of said circuit blocks.

A decode circuit for a memory comprising:

• a predecoder for predecoding a part of address signals of plural bits and outputting a predecoded signal as a block selecting signal;
• and
• plural circuit blocks to be selected in accordance with said block selecting signal of said predecoder,
• wherein each of said circuit blocks includes:
• plural logic circuits, each having the same configuration and including plural transistors, for decoding remaining address signals which are not predecoded by said predecoder when said circuit block is selected;
• and
• a switching circuit for connecting said plural logic circuits with a predetermined power supply,
• said switching circuit includes a single merged transistor formed by merging transistors having the same function of said plural logic circuits, and
• said merged transistor of said switching circuit has a threshold voltage higher than a threshold voltage of another transistor included in each of said logic circuits and receives, at a gate thereof, said block selecting signal of said predecoder.