Decode circuit for use in semiconductor memory device
AssigneeNEC Corporation
InventorSeiichi Morigami
Life of this patent
Estimating the term…
Abstract
A decode circuit for use in a semiconductor memory device can prevent an increase of an area of X-decoder and can possess a plurality of banks with operating speed maintained. A word line selection signal makes a word line of a first bank region high level, before it makes first bank selection measure "off" to separate word line selection measure from the first bank region. Next, it makes second bank selection measure "on" to use the word line selection measure for selecting the word line of the second bank region so that one word line selection measure is used in common in terms of both the first bank region and the second bank region.
Claims8
A decode circuit comprising:
- word line selection means for selecting a word line changed into a high level and for releasing said word line when said word line has been latched;
- latching means for latching a word line selection signal outputted from said word line selection means, and for maintaining said word line at the high level;
- and
- reset means for resetting said word line from latch of said word line selection signal by said latching means, and for making said word line to be placed at a low level.
In a decode circuit which is provided between a first bank region and a second bank region of a semiconductor memory device both of which banks have a common input/output section, said decode circuit for use in said semiconductor memory device comprising:
- word line selection for selecting a word line changed into a high level and for releasing said word line when said word line has been latched;
- first bank selection means for selecting said first bank region;
- second bank selection means for selecting said second bank region;
- first latching means for latching a word line selection signal outputted from said word line selection means, and for maintaining said word line of said first bank region at the high level based on a selection signal outputted from said first bank selection means;
- second latching for latching a word line selection signal outputted from said word line selection means, and for maintaining a word line of said second bank region at the high level based on a selection signal outputted from said second bank selection means;
- first reset means for resetting the latch of said word line selection signal by said first latching means, and for making said word line of said first bank region to be placed at a low level;
- and
- second reset means for releasing the latch of said word line selection signal by said second latching means, for making said word line of said second bank region to be place at the low level.
Dependencies are inferred from the claim text.