US 5,970,016 A · Dynamic semiconductor memory device with banks capable of operating independently

Abstract

Memory cell arrays are arranged on a chip. Each memory cell array has banks. Each bank has cell array blocks. A decoder section is concentrated in the middle of the chip. The decoder section has a row decoder, a word line drive circuit decoder for selecting a word line drive circuit, a sense amplifier decoder for selecting a sense amplifier, and an equalize signal decoder for selectively supplying an equalize signal. Each of these decoders outputs a select signal. The individual banks share the decoder section. Each bank has a latch circuit for latching a select signal in pulse form supplied from the decoder section and controls the memory blocks according to each select signal latched in the latch circuit. A shared sense amplifier is provided between memory blocks in each bank. A redundancy cell array is provided for each bank.

Claims26

Dependent claims

A dynamic semiconductor memory device comprising:

cell arrays, each cell array having banks, said cell arrays being arranged in a semiconductor chip in a direction in which said banks are arranged;
decoder sections which are provided between said cell arrays, shared by said banks, and output pulse-like select signals for selecting a word line in each of said banks according to a row address;
latch circuits which are provided between said banks and latch the select signals from said decoder sections according to a bank activate signal for activating each bank;
and
word line drive circuits which are provided between said banks and drive word lines in each bank according to the select signals latched in said latch circuits.

2 more elements

A dynamic semiconductor memory device comprising:

cell arrays, each cell array having banks, said cell arrays being arranged in a semiconductor chip in a direction in which said banks are arranged, and each bank having memory blocks in a direction perpendicular to the direction in which said banks are arranged;
decoder sections which are provided between said cell arrays and shared by said banks, said decoder sections having row decoders for outputting pulse-like select signals to select a word line in each of said banks according to a row address;
word line drive signal generator circuits which are provided in said decoder sections and generate pulse-like drive signals to drive said word lines;
first wires which cross individual banks in each of said cell arrays and transfer the select signals;
second wires which cross the individual banks in each of said cell arrays and transfer the drive signals;
word line drive circuits which are provided between said banks and drive the word lines in each of said memory blocks;
first latch circuits which are provided between said banks, latch the select signals transferred through said first wires according to bank activate signals to activate each bank, and activate said word line drive circuits according to the latched select signals;
second latch circuits which are provided between said banks and latch the drive signals transferred through said second wires according to the bank activate signals to activate each bank;
and
word line drive voltage generator circuits which are provided between said banks and connected to said word line drive circuits and generate a drive voltage to drive said word lines according to the drive signals latched in said second latch circuits and supply the drive voltage to said word line drive circuits.

7 more elements

A dynamic semiconductor memory device comprising:

cell arrays, each cell array having banks, and arranged in a semiconductor chip in a direction in which said banks are arranged;
memory blocks which are provided in each of said banks and arranged in a direction perpendicular to the direction in which said banks are arranged;
sense amplifiers, which are provided between adjacent memory blocks in each of said banks and are shared by the adjacent memory blocks, that sense signals read from said memory blocks;
decoder sections, which are provided between said cell arrays and shared by said banks, that output pulse-like select signals for activating said sense amplifiers according to a row address;
latch circuits which are provided between said banks and latch the select signals outputted from said row decoders according to a bank activate signal for activating each bank;
and
activate circuits which are provided between said banks and activate each of said sense amplifiers according to the select signals latched in said latch circuits.

4 more elements

A dynamic semiconductor memory device comprising:

cell arrays, each cell array having banks, and arranged in a semiconductor chip in a direction in which said banks are arranged;
memory blocks which are provided in each of said banks and arranged in a direction perpendicular to the direction in which said banks are arranged;
sense amplifiers, which are provided between adjacent memory blocks and are shared by the adjacent memory blocks, that sense signals read from said memory blocks;
transistor pairs for connecting said sense amplifiers to bit line pairs of said memory blocks;
equalize circuits for equalizing a potential of said bit line pairs;
decoder sections, which are provided between said cell arrays and shared by said banks, that output pulse-like select signals for activating said transistor pairs and said equalize circuits according to a row address;
latch circuits which are provided between said banks and latch the select signals outputted from said row decoders according to a bank activate signal for activating each bank;
and
drive circuits which are provided between said banks and drive said transistor pairs and said equalize circuits according to the select signals latched in said latch circuits.

6 more elements

Dependencies are inferred from the claim text.

Dynamic semiconductor memory device with banks capable of operating independently

Life of this patent

Dynamic semiconductor memory device with banks capable of operating independently

Life of this patent

Abstract

Claims26