Adaptive addressable circuit redundancy method and apparatus with broadcast write

A method of broadcasting a data pattern to a plurality of addressable locations normally accessed individually, said method comprising:

• intercepting a normal operation data path between a processor and said plurality of addressable locations;
• intercepting a normal operation control path including chip select signals between said processor and said plurality of addressable locations;
• driving a predetermined data pattern onto said intercepted normal operation data path to said plurality of addressable locations;
• and
• enabling, substantially simultaneously, said plurality of addressable locations.

Apparatus for broadcasting a data pattern to a plurality of addressable locations normally accessed individually, said apparatus comprising:

• means for intercepting a normal operation data path between a processor and said plurality of addressable locations;
• means for intercepting a normal operation control path including chip select signals between said processor and said plurality of addressable locations;
• means for driving a predetermined data pattern onto said intercepted normal operation data path to said plurality of addressable locations;
• and
• means for enabling, substantially simultaneously, said plurality of addressable locations.

An integrated circuit adapted to be installed on a larger integrated circuit device, said integrated circuit comprising:

• an interface to a processor on said larger integrated circuit device;
• a control module adapted to select access to at least two of a plurality of addressable circuits of said larger integrated circuit device substantially simultaneously, said at least two of said plurality of addressable circuits being accessed individually during normal operations of said larger integrated circuit device;
• and
• a log module adapted to maintain reliability information of said plurality of addressable circuits wherein said log module provides said reliability information to said processor through said interface.

A method for reducing memory test time by using an on-chip broadcast, said method comprising:

• intercepting a normal operation data path between a processor and a plurality of addressable circuits;
• intercepting a normal operation control path including a plurality of chip select signals between said processor and said plurality of addressable circuits;
• driving a predetermined data pattern onto said intercepted normal operation data path to said plurality of addressable locations;
• and
• enabling, substantially simultaneously, said plurality of addressable circuits using said normal operation control path.