Non-volatile semiconductor memory device having a memory cell capable of establishing multi-level information and data writing method thereof

A semiconductor memory device, comprising:

• first and second memory cell transistors each taking one of a plurality of threshold values to be stored in accordance with a plurality of data by controlling a voltage between a control gate and a source thereof;
• a word line connected to control gates of said first and second memory cell transistors in common;
• and
• a control circuit which supplies a first source voltage to a source of said first memory cell transistor and a first drain voltage to a drain of said first memory cell transistor when a first data is stored in said first memory cell transistor,
• wherein when a second data which is different from said first data is stored in said first memory cell transistor, a second source voltage, which is different from said first source voltage, is supplied to a source of said second memory cell transistor, and a second drain voltage, which is different from said first drain voltage, is supplied to a drain of said second memory cell transistor.

A semiconductor memory device comprising:

• a memory cell array;
• first and second memory cell blocks in said memory cell array, said first memory cell block having a first line, a second line, a word line, and a first memory cell transistor, said first memory cell transistor having a first control gate coupled to said word line, a first source coupled to said first line and a first drain coupled to said second line, said second memory block having a third line, a fourth line, said word line, and a second memory cell transistor, said second memory cell transistor having a second control gate coupled to said word line, a second source coupled to said third line and a second drain coupled to said fourth line;
• a first voltage generator supplying said first line with a first voltage corresponding to first write information;
• a second voltage generator supplying said third line with a second voltage corresponding to second write information;
• a third voltage generator supplying said second line with a third voltage corresponding to said first write information;
• a fourth voltage generator supplying said fourth line with a fourth voltage corresponding to said second write information;
• and
• a decoder which supplies a word line voltage to said word line at a write mode, said word line voltage being higher than said first voltage, said second voltage, said third voltage, and said fourth voltage.

A writing method in a semiconductor memory device having first through fourth memory cell transistors, each including control gates coupled to a word line commonly, comprising the steps of:

• activating said word line;
• supplying a first voltage corresponding to first write data to a first source of said first memory cell transistor from a first source voltage generator and a second voltage to a first drain of said first memory cell transistor from a first drain voltage generator during a first period;
• supplying a third voltage corresponding to second write data to a second source of said second memory cell transistor from a second source voltage generator and a fourth voltage to a second drain of said second memory cell transistor from a second drain voltage generator during said first period;
• supplying a fifth voltage corresponding to third write data to a third source of said third memory cell transistor from said first source voltage generator and a sixth voltage to a third drain of said third memory cell transistor from said first drain voltage generator during a second period;
• and
• supplying a seventh voltage corresponding to fourth write data to a fourth source of said fourth memory cell transistor from said second source voltage generator and an eighth voltage to a fourth drain of said fourth memory cell transistor from said second drain voltage generator during said second period;
• electrically, connecting said first source with said first source voltage generator, connecting said second source with said second source voltage generator, connecting said first drain with said first drain voltage generator, and connecting said second drain with said second drain voltage generator, when a first control signal is activated, during said first period;
• electrically, preventing said third source from connecting with said second source voltage generator, preventing said fourth source from connecting with said first source voltage generator, preventing said third drain from connecting with said second drain voltage generator, and preventing said fourth drain from connecting with said first drain voltage generator, when a second control signal is disactivated, during said first period;
• electrically, connecting said third source with said second source voltage generator, connecting said fourth source with said first source voltage generator, connecting said third drain with said second drain voltage generator, and connecting said fourth drain with said first drain voltage generator, when said first control signal is disactivated, during said second period;
• and
• electrically, preventing said first source from connecting with said first source voltage generator, preventing said second source from connecting with said second source voltage generator, preventing said first drain from connecting with said first drain voltage generator, and preventing said second drain from connecting with said second drain voltage generator, when said second control signal is activated, during said second period.

A semiconductor memory device comprising:

• a plurality of pairs of drain and source lines;
• a plurality of block selection lines;
• a plurality of groups of word lines;
• a plurality of memory blocks, each of said memory blocks arranged at each crossing points of said pairs of drain and source lines and said block selection lines so that each of said memory blocks has the respective one of said pairs of drain and source lines, the respective one of said block selection lines, and each of said memory blocks having the respective one of groups of word lines;
• each of said memory blocks having a plurality of memory cell transistors, each of said memory cell transistors having drain commonly electrically connected to said drain line therein when said block selection line is activated, source commonly electrically connected to said source line therein when said block selection line is activated, and gate connected to the respective word line therein;
• a source voltage generator supplying a source voltage, corresponding to write data, to one of said plurality of source lines, said source voltage is lower than a word line voltage supplied to said word line at a write mode;
• and
• a drain voltage generator supplying a drain voltage to one of said plurality of drain lines, said drain voltage is lower than said word line voltage.