Power source design for embedded memory
AssigneeUnited Microelectronics Corp.
InventorsChian-Gauh Shih, Cheng-Ju Hsieh, Jaris Yeh, Jacob Chen
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Abstract
A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.
Claims12
A power source design for embedded memory, wherein the embedded memory includes a dynamic random access memory (DRAM), a logic unit and a testing mode circuit with input/output ports, comprising:
- designing a first power source group linking the DRAM, a second power source group linking the logic unit and a third power source group linking the testing mode circuit with input/output ports during the silicon chip stage;
- and
- joining the first power source group, the second power source group and the third power source group during the packaging stage.
An embedded memory, comprising:
- a dynamic random access memory having a first power source group;
- a logic unit having a second power source group;
- and
- a testing mode circuit with input/output ports having a third power source group, wherein the first power source group, the second power source group and the third power source group are independently connected during the silicon chip stage, while the first power source group, the second power source group and the third power source group are joined together during the packaging stage.
Dependencies are inferred from the claim text.