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US 5,970,009 AGranted
Reduced stand by power consumption in a DRAM
AssigneesSiemens Aktiengesellschaft, International Business Machines Corporation
InventorsHeinz Hoenigschmid, Richard L. Kleinhenz, Jack A. Mandelman
Life of this patent
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Abstract
Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.
Claims18
A method for reducing standby current in a dynamic random access memory (DRAM) comprising:
- determining whether the DRAM is in standby or normal mode of operation;
- switching off a first power source to an array in the DRAM if the DRAM is in standby mode;
- maintaining the first power source to the array if the DRAM is in a normal mode;
- and
- outputting from a NOR gate first and second signals for respectively turning the first power source on and off wherein inputs to the NOR gate include a column address strobe before a row address strobe (CBR) signal and a row address strobe counter signal.
2 more elements
A semiconductor memory having a standby mode and a normal mode comprising:
- a logic circuit for monitoring refresh signals to determine whether the memory is in standby or normal mode of operation;
- a regulating circuit for switching off a first power source and a second power source to an array in the DRAM if the DRAM is in standby mode wherein the first power source and the second power source are maintained to the array if the DRAM is in normal mode, the first source and second power source for causing a cumulative potential difference between a p-well and an n-well adjacent to a trench capacitor in the array.
A dynamic random access memory (DRAM) having a standby mode and a normal mode comprising:
- an array of memory cells, each memory cell having a storage node for storing charge;
- a first power source for maintaining a first potential in a first region located externally to the storage node;
- means for determining whether the DRAM is in standby or normal mode of operation;
- and
- switching means for turning off the first power source to the array in the DRAM if the DRAM is in standby mode in accordance with a first signal and maintaining the first power source to the array if the DRAM is in normal mode in accordance with a second signal such that leakage from the storage node is reduced during the standby mode;
- and
- the first and second signals being output from a NOR gate wherein inputs to the NOR gate include a column address strobe before a row address strobe (CBR) signal and a row address strobe counter signal.
4 more elements
A semiconductor memory having a standby mode and a normal mode comprising:
- a logic circuit for monitoring refresh signals to determine whether the memory is in standby or normal mode of operation;
- a regulating circuit for switching off a first power source to an array in the DRAM if the DRAM is in standby mode wherein the first power source is maintained to the array if the DRAM is in normal mode, the regulating circuit includes a first switch for coupling the first power source to the array when turned on by a first signal and a second switch for coupling the first power source to a ground when turned on by a second signal;
- and
- a NOR gate included in the logic circuit wherein inputs to the NOR gate include a column address strobe before a row address strobe (CBR) signal and a row address strobe counter signal and an output of the NOR gate provides the first and the second signals.
1 more element
Dependencies are inferred from the claim text.