Semiconductor integrated circuit device
AssigneeKabushiki Kaisha Toshiba
InventorShinichiro Shiratake
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Abstract
A semiconductor memory device having a sense amplifier, comprises an n-type sense amplifier formed of an nMOS transistor with a source connected to a bit line and a gate connected to an inverted bit line, and an nMOS transistor with a source connected to the inverted bit line and a gate connected to the bit line. In activating the n-type sense amplifier, the voltage of a control signal line is set to a voltage Vss2 lower than a ground voltage Vss. In restoring data in a capacitor of a memory cell, the voltage of the control signal line is set to the ground voltage Vss. With this setting, the sense amplifier can operate at an ultra-low voltage and can ensure a satisfactory operation margin.
Claims18
A semiconductor integrated circuit device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells each having a capacitor capable of storing data having one of at least two voltages, and a transfer gate transistor for controlling connection between said capacitor and said bit line in accordance with a voltage of said word line;
- an n-type sense amplifier having a first n-channel FET with a drain connected to a first bit line of said plurality of bit lines and a gate connected to a second bit line, and a second n-channel FET with a drain connected to said second bit line and a gate connected to said first bit line;
- an n-type sense amplifier driver for applying an n-type sense amplifier activating voltage to sources of said first and second n-channel FETs;
- and
- a sense amplifier controller for setting the n-type sense amplifier activating voltage applied by said n-type sense amplifier driver to a first voltage lower than the lowest voltage of data stored in said capacitor in activating said n-type sense amplifier, and setting the n-type sense amplifier activating voltage applied by said n-type sense amplifier driver to a second voltage substantially equal to the lowest voltage of data stored in said capacitor in restoring data in said capacitor of said memory cell.
A semiconductor integrated circuit device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells each of which is arranged at an intersection of said word line and said bit line, and has a capacitor capable of storing data having one of at least two voltages, and a transfer gate transistor for controlling connection between said capacitor and said bit line in accordance with a voltage of said word line;
- an n-type sense amplifier having a first n-channel FET with a drain connected to a first bit line of said plurality of bit lines and a gate connected to a second bit line, and a second n-channel FET with a drain connected to said second bit line and a gate connected to said first bit line;
- and
- a p-type sense amplifier having a first p-channel FET with a drain connected to said first bit line and a gate connected to said second bit line, and a second p-channel FET with a drain connected to said second bit line and a gate connected to said first bit line, and in which data stored in said capacitor is transmitted to either one of said first and second bit lines precharged to a precharge voltage which is an intermediate voltage of a power supply voltage to generate a small voltage difference between said first and second bit lines, a first voltage which is lower than a low voltage of the power supply voltage is applied to sources of said first and second n-channel FETs to discharge one of the first and second n-channel FETs which has a lower voltage after said data transmission from said capacitor, the voltage difference between said first voltage and voltage of either one of said first and second bit lines before said discharging is larger than threshold voltages of said first and second n-channel FTEs, the other of said first and second bit lines is charged through one of said p-channel FETs of which gate is connected to one of said first and second bit lines which has a lower voltage after said data transmission from said capacitor, thereby amplifying the small voltage difference generated between said first and second bit lines.
Dependencies are inferred from the claim text.